数字电路8.1.ppt

1、1 1Chapter 8 Chapter 8 Sequential LogicSequential LogicDesign PrDesign Practicesactices（时序逻辑设计实践）（时序逻辑设计实践）8.1 8.1 Sequential-Circuit Documentation Sequential-Circuit Documentation Standards Standards General RequirementsLogic SymbolsState-Machine Descriptionsword,state table,state diagram,transitio

2、n list,etc.Timing Diagrams and Specifications(了解了解,自学自学.)CLOCKHtLtclktflip-flop outputsffpdtcombtCombinational outputsflip-flop inputsholdtsetuptsetup-time marginclkffpd(max)comb(max)setuptttthold-time marginffpd(min)comb(min)holdttt+Detailed timing diagram:Detailed timing diagram:Functional timing

3、diagram:Functional timing diagram:8.2 8.2 Latches and Flip-FlopsLatches and Flip-FlopsSSISSI Latches and Flip-FlopsLatches and Flip-Flops1Q 1Q2Q2Q3Q3Q4Q4Q1,2C1D2D3,4C3D4D74x375PRD Q CLK QCLR74x74PRJ Q CLK K QCLR74x109 74x74:two D flip-flops 74x109:two J-K flip-flops 74x375:four D latches+5VSW_LDSWpu

4、shSW_LDSWpushfirst contactbounceSW_LDSWIdeal condition Switch Switch DebouncingDebouncing（开关消抖）（开关消抖）SW_LSW0011SW_LSW0011push0011SW_LSW0011SW_LSW1100 Use a bistable element for debouncingSW_LSWDSWpushDSWS QR Q+5V Use an S-R latch for debouncing存在存在”瞬时短路瞬时短路”的情况的情况!ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN

5、1EN2_LEN3_LSRC0SRC1SRC2P0P1P7SDATABus holder circuitBus holder circuit（总线保持电路）（总线保持电路）MultibitMultibit Registers and Latches Registers and LatchesMultibit Latche：Multi-latches with a common enable input.Multibit Register：Multi-flip-flops with a common clock input.(often used to store a collection of

6、 related bits)74x175:4-bit register(有异步清零端，含低电平有效输出有异步清零端，含低电平有效输出)74x174:6-bit register(有异步清零端，无低电平有效输出有异步清零端，无低电平有效输出)74x374:8-bit register(含三态输出，含三态输出，OE_L为为”输出使能输出使能”)74x373:8-bit latch (374的变种，电平有效的变种，电平有效)74x273:8-bit register(374的变种，不含三态输出，有清零端的变种，不含三态输出，有清零端)74x377:8-bit register(374的变种，不含三态

7、输出，有时钟使的变种，不含三态输出，有时钟使 能输入能输入.)Commonly MSI Registers and Latches 4-bit register 74x1751D2D3D4DCLKCLR_L 6-bit register 74x174three-state outputOEoutput enable 8-bit register 74x374寄存器和锁存器的区别？寄存器和锁存器的区别？寄存器寄存器374：边沿触发；：边沿触发；锁存器锁存器373：C有效期间，输出跟随输入变化。有效期间，输出跟随输入变化。(电平有效电平有效)74x3748-bit register74x3738-bit latch7474x377x377(clock enable)7474x273x273(asynchronous clear)CLK7474x374x374(output enable)7474x377 x377(clock enable)ENEN2-to-1 MUXEN可用于屏蔽时钟有效沿可用于屏蔽时钟有效沿