电子设计自动化基础-7综合基础知识课件.ppt

1、综合基本知识李晓明内容模块综合过程关键约束介绍约束文件实例DC图形界面综合的过程Synthesis =residue=16h0000;if(high_bits=2b10)residue=state_tableindex;else state_tableindex=16h0000;HDL SourceGeneric Boolean(GTECH)TranslateTarget TechnologyOptimize+MapTranslation+Optimization+MappingSynthesis Is Constraint-DrivenDesign Compiler 对设计进行优化，以达到你

2、的设计目标对设计进行优化，以达到你的设计目标LargeAreaSmallShort Delay High设计者设计者设定目标设定目标(through constraints)write模块综合过程模块综合过程gtech.dbGTECH my_chip.v(hd)writeOPTIMIZATION+MAPPINGsourceDC_MEMORYTRANSLATIONscriptsconstraints.tclmappedmy_chip.dbmy_chip.edifcompileDC_MEMORYMY_CHIPcore_slow.dbtarget_libraryHDL sourceunmappedm

3、y_chip.dbread_dbanalyze/elaborateY=A+BMY_CHIPread_vhdl read_verilog工艺库cell(OR2_3)area:8.000;pin(Y)direction:output;timing()related_pin:A;timing_sense:positive_unate;rise_propagation(drive_3_table_1)values(0.2616,0.2608,0.2831,.)rise_transition(drive_3_table_2)values(0.0223,0.0254,.).function:(A|B);m

4、ax_capacitance:1.14810;min_capacitance:0.00220;pin(A)direction:input;capacitance:0.012000;.Cell nameCell AreaPin A-Pin Y nominal delays(look-up table)Design Rules for Output PinElectrical Characteristics of Input PinsPin Y functionalityY=A|BtABYExample of a cell description in.lib Formatmodule TOP(A

5、,B,C,D,CLK,OUT1);input A,B,C,D,CLK;output 1:0 OUT1;wire INV1,INV0,bus1,bus0;ENCODER U1(.AIN(A),.Q1(bus1);INV U2(.A(BUS0),.Z(INV0),U3(.A(BUS1),.Z(INV1);REGFILE U4(.D0(INV0),.D1(INV1),.CLK(CLK);endmodule设计目标PinCellReferencePortDesignClockNetD0 Q1:0D1REGFILEU4OUT1:0INV0INV1AINBINCINDINQ0Q1ENCODERINVINV

6、U1U2ABCDCLKBUS0BUS1ABCDCLKU3TOPPinCLK设计目标设计目标ClockReference and DesignDesignCellNetPortDesigns:TOP,ENCODER,REGFILEReferences:ENCODER,REGFILE,INVCells:U1,U2,U3,U4Setting Design Rule Constraintsthe most commonly specified design rule constraints:nTransition timenFanout loadnCapacitanceSetting Transiti

7、on Time ConstraintsThe transition time of a net is the time required for its driving pin to change logic values.nDesign Compiler calculates the transition time for each net by multiplying the drive resistance of the driving pin by the sum of the capacitive loads connected to the driving pin.Setting

8、Fanout Load ConstraintsThe maximum fanout load for a net is the maximum number of loads the net can drive.nThe fanout load value does not represent capacitance;it representsthe weighted numerical contribution to the total fanout load.Setting Capacitance ConstraintsThe transition time constraints do

9、not provide a direct way to control the actual capacitance of nets.nThe set_max_capacitance command sets a maximum capacitance for the nets attached to the named ports or to all the nets in a design by setting the max_capacitance attribute on the specified objects.同步设计（同步设计（Synchronous Design）D Q QB

10、D Q QBD Q QBD Q QBClk TO_BE_SYNTHESIZEDFF1FF2FF3FF4MNXSTWhat information must you provide to constrain all the register-to-register paths in your design?定义时钟User MUST Define:lClock Source(port or pin)lClock PeriodPeriodClkN X S D QD Q TO_BE_SYNTHESIZEDFF2FF3User may also define:lDuty CyclelOffset/Sk

11、ewlClock NameClk1 Clock CycleCommands to Set Timing ConstraintsSet Timing ConstraintsMultiple clocks:npay close attention to the common base period of the clocks.The common base period is the least common multiple of all the clock periods.nFor example,if you have clock periods of 10,15,and 20,the co

12、mmon base period is 60.Virtual Clock:nIn some cases,a system clock might not exist in a block.You can use the create_clock-name command to create a virtual clock for modeling clock signals present in the system but not in the block.n By creating a virtual clock,you can represent delays that are rela

13、tive to clocks outside the block.Clock Network DelayClock Network DelaynBy default,Design Compiler assumes that clock networks have no delay(ideal clocks).nUse the set_clock_skew command to specify timing information about the clock network delay(either estimated or actual delay)nUse the-propagated

14、option:specify that you want Design Compiler to calculate clock network delay by propagating times through the clock network.nUse the-plus_uncertainty(-minus_uncertainty)options:to add some margin of error into the system to account for variances in the clock network resulting from layout.set_input_

15、delayTO_BE_SYNTHESIZEDAClk(50 MHz)EXTERNAL CIRCUITcreate_clock-period 20 get_ports Clkset_dont_touch_network get_clocks Clkset_input_delay-max 7.4-clock Clk get_ports ADQNClkCLK-OUTPUT7.4 ns(worst)U1set_output_delaycreate_clock-period 20 get_ports Clkset_dont_touch_network get_clocks Clkset_output_d

16、elay-max 7.0-clock Clk get_ports BClkSD QTO_BE_SYNTHESIZEDBEXTERNAL CIRCUITSetup Requirement:7.0 nsClock(50 MHz)U3Specifying Combinational Path DelayFor purely combinational delays that are not bounded by a clock periodnuse the set_max_delay and set_min_delay commands to define the maximum and minim

17、um delays for the specified paths.nA common way to produce this type of asynchronous logic in HDL code is to use asynchronous sets or resets on latches and flip-flops.Because the reset signal crosses several blocks,constrain this signal at the top level.Specifying Timing ExceptionsUse timing excepti

18、ons to constrain or disable asynchronous paths or paths that do not follow the default single-cycle behavior.nBe aware that specifying numerous timing exceptions can increase the compile runtime.nYou can specify the following conditions by using timing exception commands:wFalse paths(set_false_path)

19、wMinimum delay requirements(set_min_delay)wMaximum delay requirements(set_max_delay)wMulticycle paths(set_multicycle_path)The fifth path(U1/G to U1/D)is a functional false path because normal operation never requires simultaneous writing and reading of the configuration register.Setting Area Constra

20、intsDesign area consists of the areas of each component and net.The following components are ignored when Design Compiler calculates design area:nUnknown componentsnComponents with unknown areasnTechnology-independent generic cells描述环境属性set_driving_cellset_loadset_operating_conditionsset_wire_load_m

21、odel TO_BE_SYNTHESIZED估计电容负载为了精确计算输出电路的时序，DC需要知道输出元件驱动的总电容set_load 命令可定义端口外部电容负载:缺省情况下,DC假定端口外部电容负载为 0set_load expr load_of my_lib/inv1a0/A*3 OUT1AOUT1AAOUT1AN2Aset_load load_of my_lib/and2a0/A get_ports OUT1B估计输入端驱动强度为了精确计算输出电路的时序，DC需要知道信号到达输入端的转换时间set_driving_cell命令可定义驱动输入端的外部元件:缺省值为0dc_shell-t se

22、t_driving_cell-lib_cell and2a0 get_ports IN1ND2IN1 TO_BE_SYNTHESIZEDOperating Conditions:Name Library Process Temp Volt -typ_25_1.80 my_lib 1.00 25.00 1.80 slow_125_1.62 my_lib 1.00 125.00 1.62 fast_0_1.98 my_lib 1.00 0.00 1.98 设置工作环境缺省：对于一个设计，没有指定的工作环境（operating conditions）使用 report_lib libname 查看v

23、endor-supplied 工作环境dc_shell-t set_operating_conditions-max“slow_125_1.62”quotes are optional设置工作环境，键入:线负载模型线负载模型（Wire Load Model）线负载模型(WLM)是对连线的RC寄生参数的估计，基于连线的扇出（fanout）:n模型由vendor提供nvendor 采用该工艺制造其他芯片时，得到统计值，由此得到线负载模型的估计值Wire Load Model:标准格式Name :160KGATESLocation :ssc_core_slowResistance :0.000271

24、Capacitance :0.00017Area :0Slope :50.3104Fanout Length-1 31.44 2 81.75 3 132.07 4 182.38 5 232.68 Example:Standard FormatR per unit lengthC per unit lengthExtrapolation slopeTime Unit :1nsCapacitive Load Unit :1.000000pfPulling Resistance Unit:1kilo-ohmOptimizing Your DesignResolving Multiple Instan

25、cesIf your design references any design more than once,you must resolve these multiple instances before running the compile command.nThe uniquify method:This method uses the uniquify command to create a copy of the design for each instance.nThe compile-once-dont-touch method:This method uses the set

26、_dont_touch command to preserve the subdesign during optimization.nThe ungroup method:This method uses the ungroup command to remove the hierarchy.uniquify command to copy and rename the design for each instance.ungroup has the same effect as the uniquify method(making unique copies of the design)bu

27、t also removes levels of hierarchy.Optimizing Random LogicIf the default compile does not give the desired result for your random logic design,try the following techniques.If the first technique does not give the desired results,use the second technique,and so on,until you obtain the desired results

28、.nFlatten the design before structuring:dc_shell set_flatten truedc_shell set_structure truedc_shell compileIncrease the flattening effort:dc_shell set_flatten true-effort mediumdc_shell compileOptimizing Structured LogicIf the default compile does not give the desired result for your structured log

29、ic design,try the following techniques.If the first technique does not give the desired results,try the second one.nMap the design with no flattening or structuring.Enterdc_shell set_structure falsedc_shell compilenFlatten with structuring.Enterdc_shell set_flatten truedc_shell set_structure truedc_

30、shell compile例：例：Adder16.v/*16-Bit Adder Module*/module Adder16(ain,bin,cin,sout,cout,clk);output 15:0 sout;output cout;input 15:0 ain,bin;input cin,clk;wire 15:0 sout_tmp,ain,bin;wire cout_tmp;reg 15:0 sout,ain_tmp,bin_tmp;reg cout,cin_tmp;always(posedge clk)begincout=cout_tmp;sout=sout_tmp;ain_tmp

31、=ain;bin_tmp=bin;cin_tmp=cin;endassign cout_tmp,sout_tmp=ain_tmp+bin_tmp+cin_tmp;endmodule约束文件实例（run.scr）一个约束文件，采用自顶向下的编译策略，对Adder16.v进行优化/*specify the libraries*/指定库target_library=my_lib.dbsymbol_library=my_lib.sdblink_library=*+target_library/*read the design*/读入设计read-format verilog Adder16.v/*de

32、fine the design environment*/定义设计环境set_operating_conditions WCCOMset_wire_load 10 x10set_load 2.2 soutset_load 1.5 coutset_driving_cell-cell FD1 all_inputs()set_drive 0 clk约束文件实例（Cont）/*set the optimization constraints*/设置优化约束create_clock clk-period 10set_input_delay-max 1.35-clock clk ain,binset_in

33、put_delay-max 3.5-clock clk cinset_output_delay-max 2.4-clock clk coutset_max_area 0/*map and optimize the design*/映射并优化设计Uniquify/为每个例化元件映射一个设计Compile/执行综合并优化/*analyze and debug the design*/分析并调试设计report_constraint-all_violatorsreport_area/*save the design database*/保存设计数据write-format db-hierarchy-output Adder16.db约束的运行方式用户可以采用如下几种方法执行命令：a)进入dc_shell，并逐个键入命令 b)进入dc_shell，并执行脚本文件，采用include命令（dcsh模式）或source命令（Tcl模式）。如假设上面的脚本文件称作run.scr，则在dcsh模式下运行dc_shell include run.scr c)在UNIX命令行模式下运行脚本，如%dc_shell-f run.scrDesign Analyzer图形界面读入设计时钟约束时钟约束优化优化输出报告输出报告Thank you!