静态时序分析基本原理和时序分析模型课件.ppt

1、 2009 Altera Corporation1Quartus II Software Design Series:Timing Analysis-Timing analysis basics 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation2ObjectivesnDisplay a complete understanding of timing analysis 2009 Altera

2、 CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation3How does timing verification work?nEvery device path in design must be analyzed with respect to timing specifications/requirements-Catch timing-related errors faster and easier than g

3、ate-level simulation&board testingnDesigner must enter timing requirements&exceptions-Used to guide fitter during placement&routing-Used to compare against actual results INCLKOUTDQCLRPREDQCLRPREcombinational delaysCLR 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and

4、 MegaCore are trademarks of Altera Corporation4Timing Analysis BasicsnLaunch vs.latch edgesnSetup&hold timesnData&clock arrival timenData required timenSetup&hold slack analysisnI/O analysisnRecovery&removalnTiming models 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,

5、and MegaCore are trademarks of Altera Corporation5Path&Analysis TypesThree types of Paths:1.Clock Paths2.Data Path3.Asynchronous Paths*Clock PathsAsync PathData PathAsync PathDQCLRPREDQCLRPRETwo types of Analysis:1.Synchronous clock&data paths2.Asynchronous*clock&async paths*Asynchronous refers to s

6、ignals feeding the asynchronous control ports of the registers 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation6Launch&Latch EdgesCLKData ValidDATALaunch Edge:the edge which“launches”the data from source registerLatch Edg

7、e:the edge which“latches”the data at destination register(with respect to the launch edge,selected by timing analyzer;typically 1 cycle)2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation7Setup&HoldSetup:The minimum time dat

8、a signal must be stableBEFORE clock edgeHold:The minimum time data signal must be stableAFTER clock edgeDQCLRPRECLKThValidDATATsuCLKDATATogether,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.2009 Altera CorporationAltera,Stratix,Ar

9、ria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation8Data Arrival TimeData Arrival Time=launch edge+Tclk1+Tco+TdataCLKREG1.CLKTclk1Data ValidREG2.DTdataLaunch EdgeData ValidREG1.QTconThe time for data to arrive at destination registers D inputREG1PRED QCLRREG2PRED

10、QCLRComb.LogicTclk1TCOTdata 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation9Clock Arrival TimeClock Arrival Time=latch edge+Tclk2 CLKREG2.CLKTclk2Latch EdgenThe time for clock to arrive at destination registers clock inp

11、utREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation10Data Required Time-SetupData Required Time=Clock Arrival Time-Tsu-Setup Uncertainty CLKREG2.CLKTclk2Latch EdgenThe minimum time

12、 required for the data to get latched into the destination registerTsuData ValidREG2.DData must be valid hereREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2Tsu 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation11Data Required Tim

13、e-HoldData Required Time=Clock Arrival Time+Th+Hold Uncertainty CLKREG2.CLKTclk2Latch EdgenThe minimum time required for the data to get latched into the destination registerThData mustremain validto hereData ValidREG2.DREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2Th 2009 Altera CorporationAltera,Strati

14、x,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation12Tclk2Setup SlackREG2.CLKnThe margin by which the setup timing requirement is met.It ensures launched data arrives in time to meet the latching requirement.TsuCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidRE

15、G1.QTco Setup SlackLaunch EdgeLatch EdgeREG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdataTclk2Tsu 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation13Setup Slack(contd)Positive slack-Timing requirement metNegative slack-Tim

16、ing requirement not met Setup Slack=Data Required Time Data Arrival Time 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation14Hold SlackREG2.CLKTclk2nThe margin by which the hold timing requirement is met.It ensures latch da

17、ta is not corrupted by data from another launch edge.ThCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidREG1.QTcoHoldSlackLatch EdgeNext Launch EdgeREG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdataTclk2Th 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are tr

18、ademarks of Altera Corporation15Hold Slack(contd)Positive slack-Timing requirement metNegative slack-Timing requirement not met Hold Slack=Data Arrival Time Data Required Time 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporat

19、ion16FPGA/CPLD or ASSPASSP or FPGA/CPLDI/O Analysis nAnalyzing I/O performance in a synchronous design uses the same slack equations-Must include external device&PCB timing parametersreg1PRED QCLRreg2PRED QCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCData Arrival PathData Arrival PathData Required Path*Represen

20、ts delay due to capacitive loading 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation17Recovery&RemovalRecovery:The minimum time an asynchronous signal mustbe stable BEFORE clock edgeRemoval:The minimum time an asynchronous

21、 signal mustbe stable AFTER clock edgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation18Asynchronous=Synchronous?nAsynchronous control signal source is assumed synchronous-Slack equat

22、ions still applyldata arrival path=asynchronous control pathlTsu Trec;Th Trem-External device&board timing parameters may be needed(Ex.1)ASSPreg1PRED QCLRFPGA/CPLDreg2PRED QCLROSCFPGA/CPLDreg1PRED QCLRreg2PRED QCLRExample 1Example 2Data arrival pathData arrival pathData required pathData required pa

23、th 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation19Why Are These Calculations Important?nCalculations are important when timing violations occur-Need to be able to understand cause of violationnExample causes-Data path

24、too long-Requirement too short(incorrect analysis)-Large clock skew signifying a gated clock,etc.nTimeQuest timing analyzer uses them-Equations to calculate slack-Terminology(launch and latch edges,Data Arrival Path,Data Required Path,etc.)in timing reports 2009 Altera CorporationAltera,Stratix,Arri

25、a,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation20Timing Models in DetailnQuartus II software models device timing at two PVT conditions by default-Slow Corner ModellIndicates slowest possible performance for any single pathlTiming for slowest device at maximum o

26、perating temperature and VCCMIN-Fast Corner ModellIndicates fastest possible performance for any single pathlTiming for fastest device at minimum operating temperature and VCCMAXnWhy two corner timing models?-Ensure setup timing is met in slow model-Ensure hold timing is met in fast modellEssential

27、for source synchronous interfacesnThird model(slow,min.temp.)available only for 65 nm and smaller technology devices(temperature inversion phenomenon)2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation21Generating Fast/Slow

28、NetlistnSpecify one of the default timing models to be used when creating your netlistnDefault is the slow timing netlistnTo specify fast timing netlist-Use-fast_model option with create_timing_netlist command-Choose Fast corner in GUI when executing Create Timing Netlist from Netlist menu-CANNOT se

29、lect fast corner from Tasks Pane 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation22Specifying Operating Conditions nPerform timing analysis for different delay models without recreating the existing timing netlistnTakes p

30、recedence over already generated netlistnRequired for selecting slow,min.temp.model and other models(industrial,military,etc.)depending on devicenUse get_available_operating_conditions to see available conditions for target device 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios

31、,Quartus,and MegaCore are trademarks of Altera CorporationReference DocumentsnQuartus II Handbook,Volume 3,Chapter 7 The Quartus II TimeQuest Timing Analyzerhttp:/ Start Tutorial http:/ 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Alter

32、a CorporationReference DocumentsnSDC and TimeQuest API Reference Manual-http:/ 481:Applying Multicycle Exceptions in the TimeQuest Timing Analyzer-http:/ 433:Constraining and Analyzing Source-Synchronous Interfaces-http:/ 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,

33、and MegaCore are trademarks of Altera Corporation25Instructor-Led TrainingWith Alteras instructor-led training courses,you can:Listen to a lecture from an Altera technical training engineer(instructor)Complete hands-on exercises with guidance from an Altera instructor Ask questions&receive real-time

34、 answers from an Altera instructor Each instructor-led class is one or two days in length(8 working hours per day).Online TrainingWith Alteras online training courses,you can:Take a course at any time that is convenient for youTake a course from the comfort of your home or office(no need to travel a

35、s with instructor-led courses)Each online course will take approximate one to three hours to complete.http:/ training class schedule®ister for a classLearn More Through Technical Training 2009 Altera CorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of

36、Altera Corporation26Altera Technical SupportnReference Quartus II software on-line help nQuartus II HandbooknConsult Altera applications(factory applications engineers)-MySupport:http:/ a.m.-5:00 p.m.PST)nField applications engineers:contact your local Altera sales officenReceive literature by mail:(888)3-ALTERAnFTP:nWorld-wide web:http:/-Use solutions to search for answers to technical problems -View design examples