DisplayPort-物理层测试的挑战讲课讲稿课件.ppt
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1、DisplayPort Testing ChallengesAgenda5/23/13 D i s p l a y P o rt Overview D i s p l a y P o rt 1.2 updates DisplayPort 1.2 Transmitter TestingWhats New:T2,TP3,TP3EQPhysical Layer Test Overview for DP1.2 Manual measurements/DPOJET/SDLA CTLE required in RxDP-AUX:Control DUT parameters Controls ALL TX.
2、RX devices without vendor-specific control SW Test Automation:Full Main Link testing with DP12 Automated tool setDP 1.2 Tx:Including Single-Ended and Diff Measurements(Intra-Pair Skew,AC Common Mode)Using RF Switch Integration Improved Debug Tools DisplayPort Sink/Receiver TestingBSA125C configurati
3、ons towards Rx testingJitter Impairment profile and observation times e D P testing for eDP 1.4 specification MyDP updateRef:VESA DisplayPort PHY Compliance Test Specification Version 1.2DisplayPort Technology OverviewDisplayPort is expanding its foot print Standard DisplayPort Specification Version
4、 1.2 CTS Version 1.2b Data Rates 1.62GBps,2.7Gbps and 5.4Gbps Box to Box(1,2,4 lanes)e D P Specification Version 1.4 CTG in progress Data Rates 1.62GBps,2.7Gbps and 5.4Gbps Embedded(single box Laptops)(1,2,4 lanes M y D P Specification Version 1.0 CTS Version 1.0(in approval)Data Rates 1.62GBps,2.7G
5、bps and 5.4Gbps Mobiles(1 lane)i D P Specification Version 1.1 CTG Data Rates 3.24,3.78 LVDS replacement)5/23/13DisplayPort 1.2 Overview5/23/13 T h e DisplayPort PHY Compliance Test Specification establishes a test regimen to determine compliance of DisplayPort devices-segmented into:Source Receiver
6、 Copper Cable Hybrid devices Tethered devices Test Point Definitions TP1:at the pins of the transmitter device.TP2:at the test interface on a test access fixture TP3:at the test interface on a test access TP3_EQ:TP3 with equalizer applied.TP4:at the pins of a receiving deviceDisplayPort CTS1.2bSourc
7、e Test Suite 1.EYE Diagram 2.Non Pre-Emphasis Level Verification 3.Pre-Emphasis Level Verification and Maximum Differen 4.Inter-pair Skew 5.Intra-Pair Skew 6.Differential Transition Time 7.Single Ended Rise and Fall Time Mismatch 8.Overshoot and Undershoot Test 9.Frequency Accuracy 1 0.AC Common Mod
8、e Noise 1 1.Non ISI Jitter Measurement 1 2.Total Jitter and Random Jitter Measurement 1 3.Unit Interval 1 4.Main Link Frequency Compliance Stability 1 5.Spread Spectrum Modulation Frequency 1 6.Spread Spectrum Deviation 17.dF/dt Spread Spectrum Deviation HF Variationtial Pk-Pk Output Voltage D U T C
9、onfiguration1.Bit Rates:RBR,HBR or HBR22.Patterns:D10.2,PRBS7,COMP,PLTPAT,PCTPAT3.FFE(Pre-Emphasis):0dB,3.5dB,6dB,9.5dB4.Output Levels:400mV,600mV,800mV,1200mV 5.SSC(Spread Spectrum):On/Off 6.Post-Curser2:Level 0,1,2,3 7.Lane Width,1,2,45/23/13 1 8.Dual-mode TMDS Clock(if supported)1 9.Dual-mode EYE
10、 Diagram Testing(if supported)Eye Diagram Test using Eye Compliance PatternAn Eye diagram test for 800mV,0dB pre-emphasis at TP2,TP3,TP3-EQ.5/23/13DisplayPort 1.2 CTLE Properties5/23/131.2 CTS requires adaptive application of one of three reference equalizers to the far end signal,to find a passing
11、condition.Key Elements of DisplayPort 1.2 Transition:Eye Diagram/Mask 1.2 CTS Requires Adaptive Eye Diagram Find the highest vertical eye point between.375-.625 UI at 10E-9BER Analytical tools which examine the vertical noise components project the Rn components to 10E9 BER.These tools have been pro
12、ven in the field in SATA where they have been deployed for over two years.5/23/13Key Elements of DisplayPort 1.2 Transition:dFdTWhile dFdT measurements have a unique origin emerging from the SATA and SAS specifications where the history of examining SATA dFdT has led this to become a highly recommen
13、d analysis.The dFdT contributing components will rarely appear in the normal Jitter budget due to their low frequency nature.5/23/13DisplayPort Auxiliary Channel Controller(DP-AUX)nHPDnAux Channeln S p e e d s Up Test Time-No User Interaction is Required to Change Source Output Signal or Validate Si
14、nk Silicon State or Error Countn N o Need to Learn Vendor-specific Software-A Single GUI Supports All Vendorsn V i e w&Log Decoded AUX Traffic and Hot Plug Detect(HPD)Events from the Device under Test to the DP-AUX DisplayPort AUX Controllern A b i l i ty to Read and Write DPCD Registers Supports De
15、bug Activitiesn Tektronix DP-AUX can serves as a DP1.2 Sink-Enables source to transmit the required patterns for testing.5/23/13Why use AUX channel controller in physical layer testing?Automation:DisplayPort testing is a large task!5/23/13Combination Parameters For DP1.2 TestingData Rate LanesPre-Em
16、phasis Voltage Swing Post Cursor2 SSCPatterns-3-4-4 Levels-4 Levels-4 Levels-2 Levels(SSC On and Off)-5 Supported PatternsCombination of Tests1.Differential Tests2.Single Ended Tests432 Acquired signals for DP1.2 Normative Measurements per lane.X4 lanes results in 1728 Automated Acquisitions per DUT
17、.TestWaveforms(SSC,4 Lanes Possible Combinations)Eye Diagram Test80Pre-Emphasis Test240Non-Pre-Emphasis32Total Jitter80TekExpress DisplayPort 1.2 Automation Comprehensive DisplayPort Version 1.2 Physical Layer Conformance and Compliance Verification Tool All Core DP1.2 measurements Keithley RF Switc
18、h and DP-AUX fully automated solution.Selected measurements can be applied across all test permutations(SSC,CTLEs,swing,rates,pre-emphasis,etc.)translates to 1728 measurements.DP1.2 will provide full user intervention free,automated testing.This is the killer value proposition.Factory Automation API
19、 for full product control in silicon automation systems.Complimentary Fixtures and Compliance Interconnect Channel HW defined by VESA make this package a full customer solution with no compromises.5/23/13DisplayPort 1.2 Test Selection D P 1.2Measurement selection is now provided as a function of the
20、 user specified test target capabilities.If Post Curser 2 capabilities are not present in the DUT,the measurement list will not show them.Configuration schematics and online help available for all measurements5/23/13DisplayPort 1.2 Acquisitions D P 1.2Various signal interconnect methods are supporte
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