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类型CMP化学机械研磨课件.ppt

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    关 键  词:
    CMP 化学 机械 研磨 课件
    资源描述:

    1、Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm1Chapter 12Chemical Mechanical PolishingHong Xiao,Ph.Dwww2.austin.cc.tx.us/HongXiao/Book.htmHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm2Objectives List applications of CMP Describe basic structure of a CMP system Describe slurries for ox

    2、ide and metal CMP Describe oxide CMP process.Describe metal polishing process.Explain the post-CMP cleanHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm3Overview Multi layer metal interconnection Planarization of dielectric layers Depth of focus require flat surface to achieve high resolution T

    3、he rough dielectric surface can also cause problems in metallizationHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm4MaterialsDesignMasksIC FabTestPackagingFinal TestThermal ProcessesPhoto-lithographyEtch PR stripImplant PR stripMetalizationCMPDielectric depositionWafersWafer Process FlowHong X

    4、iao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm5Tungsten CMP Tungsten has been used to form metal plugs CVD tungsten fills contact/via holes and covers the whole wafer.Need to remove the bulk tungsten film from the surface Fluorine based plasma etchback processes Tungsten CMP replaced etchbackHong X

    5、iao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm6P-EpiP-WaferMetal 3AlCu AlloyIMD 3USGMetal 4AlCuUSGSilicon NitrideAlCu AlloyN-WellP-WellBPSGn+n+p+p+STIUSGWAlCu AlloyUSGM1M2AlCuUSGWIMD 1IMD 2TiSi2TiTiN ARCWTi/TiNTi/TiNSidewall Spacer,USG PMD Barrier Nitride IMD 3Passivation 1Passivation 2PMDCMP PSG,W

    6、CMP USG,WCMP USG,WCMP USGWCMP USGCMOS IC Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm7Definition of Planarization Planarization is a process that removes the surface topologies,smoothes and flattens the surface The degree of planarization indicates the flatness and the smoothness of the sur

    7、faceHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm8 Definition of PlanarizationCompletely Conformal Film,No PlanarizationConformal and Smooth,No PlanarizationHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm9 Definition of PlanarizationPartial PlanarizationGlobal PlanarizationHong Xiao,Ph

    8、.D.www2.austin.cc.tx.us/HongXiao/Book.htm10Degrees of PlanarityPlanarityR(m)Surface Smoothing0.1 to 2.0 30Local Planarization2.0 to 10030 to 0.5Global Planarization 100 0.5Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm11Definition of PlanarityRHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book

    9、.htm12Planarization Smoothing and local planarization can be achieved by thermal flow or etchback Global planarization is required for the feature size smaller than 0.35 m,which can only be achieved by CMPHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm13Other Planarization Methods Thermal flow

    10、 Sputtering etchback Photoresist etchback,Spin-on glass(SOG)etchbackHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm14Thermal Flow Dielectric planarization Pre-metal dielectric High temperature,1000 C PSG or BPSG,become soft and start to flow due to the surface tension Smooth and local planariz

    11、ationHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm15As DepositedBPSGP-type substratep+p+N-wellP-type substrateSiO2n+n+p+p+Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm16After Thermal FlowBPSGP-type substratep+p+N-wellP-type substrateSiO2n+n+p+p+Hong Xiao,Ph.D.www2.austin.cc.tx.us/Hon

    12、gXiao/Book.htm17Etch Back Reflow temperature is too high for IMD can melt aluminum Other planarization method is needed for IMD Sputtering etch back and reactive etch backHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm18Etch Back Argon sputtering etchback chip off dielectric at corner of the g

    13、ap and taper the openings Subsequent CVD process easily fills the gap with a reasonable planarized surface Reactive ion etchback process with CF4/O2 chemistry further planarizes the surfaceHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm19CVD USGUSGAlCuSiBPSGP-type substratep+p+N-wellP-type sub

    14、straten+n+p+p+SiO2Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm20Sputtering Etch Back of USGUSGAlCuSiBPSGP-type substratep+p+N-wellP-type substraten+n+p+p+SiO2Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm21CVD USGUSGAlCuSiBPSGP-type substratep+p+N-wellP-type substraten+n+p+p+SiO2Hong

    15、 Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm22Reactive Etch Back of USGUSGAlCuSiBPSGP-type substratep+p+N-wellP-type substraten+n+p+p+SiO2Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm23Photoresist Etchback PR spin-coats can baking Planarized solid thin film on wafer surface Plasma etch

    16、process with CF4/O2 chemistry Oxide etched by F and PR by O Adjusting CF4/O2 flow ratio allows 1:1 of oxide to PR selectivity.Oxide could be planarized after etchbackHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm24After Oxide DepositedOxideMetalMetalHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXia

    17、o/Book.htm25Photoresist Coating and BakingOxidePhotoresistMetalMetalHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm26Photoresist EtchbackOxideMetalMetalHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm27Photoresist EtchbackOxideMetalMetalHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.ht

    18、m28Photoresist EtchbackOxideMetalMetalHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm29Photoresist Etchback When F etch oxide,O will be released Higher PR etch rate due to extra oxygen PR etchback cant planarize very well After the PR etchback,dielectric film surface is flatter than it is just

    19、 deposited.In some cases,more than one PR etchback is needed to achieve required flatnessHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm30SOG Etchback SOG replaces PR Advantage:some SOG can stay on the wafer surface to fill the narrow gaps PECVD USG liner and cap layer USG/SOG/USG gap fill and

    20、 surface planarization Sometimes,two SOG coat,cure and etchback processes are usedHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm31SOG EtchbackHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm32Necessity of CMP Photolithography resolution R=K1l/NA To improve resolution,NA or l DOF=K2l/2(NA

    21、)2,both approaches to improve resolution reduce DOF DOF is about 2,083 for 0.25 m and 1,500 for 0.18 m resolution.Here we assumed K1=K2,l=248 nm(DUV),and NA=0.6Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm33Necessity of CMP 0.25 m pattern require roughness 0.35 m,other methods can be usedHon

    22、g Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm34Advantages of CMP Planarized surface allows higher resolution of photolithography process The planarized surface eliminates sidewall thinning because of poor PVD step coverageHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm35Metal Line Thinnin

    23、g Due to the Dielectric StepMetal 1Metal 2IMD 1PMDSidewall ThinningHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm36Planarized Dielectric Surface,no Metal Line Thinning EffectMetal 1IMD 1PMDMetal 2Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm37Advantages of CMP Eliminate the requiremen

    24、t of excessive exposure and development to clear the thicker photoresist regions due to the dielectric steps This improves the resolution of via hole and metal line pattering processes Uniform thin film deposition Reduce required over etch time Reduce chance of undercut or substrate lossHong Xiao,Ph

    25、.D.www2.austin.cc.tx.us/HongXiao/Book.htm38PROver Exposure and Over Development Metal 2Metal 2IMD 1PRPRNeeds more exposure and developmentPossible CD loss due to more exposure and developmentHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm39Rough Surface,Long Over EtchMetal 2Metal 2IMD 1PRPRNee

    26、d a long over etch to removeHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm40Flat Surface,Short Over EtchMetal 2Metal 2PRPRVery litter over etch is requiredIMD 1Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm41Advantages of CMP CMP reduce defect density,improve yield Reducing the process

    27、 problems in thin film deposition,photolithography,and etch.CMP also widens IC chip design parameters CMP can introduce defects of its own Need appropriate post-CMP cleaningHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm42Applications of CMP STI formation Dielectric layer planarization PMD and

    28、 IMD Tungsten plug formation Deep trench capacitor Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm43Applications of CMPSTICMP USGCMP PSG,WCMP PSG,WCMP USGCMP USGCMP USGCMP WCMP WHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm44Heavily doped SiSilicon SubstrateDeep Trench CapacitorPad Oxi

    29、deHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm45Heavily doped SiSilicon SubstrateDeep Trench CapacitorNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm46Heavily doped SiSilicon SubstrateDeep Trench CapacitorNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Boo

    30、k.htm47Heavily doped SiSilicon SubstrateDeep Trench CapacitorNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm48Heavily doped SiSilicon SubstrateDeep Trench CapacitorNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm49Heavily doped SiSilicon SubstrateDeep Trenc

    31、h CapacitorNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm50Dielectric LayerHeavily doped SiSilicon SubstrateDeep Trench CapacitorNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm51Dielectric LayerHeavily doped SiSilicon SubstrateDeep Trench CapacitorNitride

    32、Pad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm52Dielectric LayerHeavily doped SiSilicon SubstrateDeep Trench CapacitorPolysiliconNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm53Dielectric LayerHeavily doped SiSilicon SubstrateDeep Trench CapacitorPolysiliconNit

    33、ridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm54Dielectric LayerHeavily doped SiSilicon SubstrateDeep Trench CapacitorPolysiliconNitridePad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm55Dielectric LayerHeavily doped SiSilicon SubstrateDeep Trench CapacitorPolysilico

    34、nPad OxideHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm56Dielectric LayerHeavily doped SiSilicon SubstrateDeep Trench CapacitorPolysiliconHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm57Applications of CMP Copper interconnection.Copper is very difficult to dry etch,Dual damascene:proc

    35、ess of choice Tungsten plug is a damascene processHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm58Applications of CMP It uses two dielectric etch processes,one via etch and one trench etch Metal layers are deposition into via holes and trenches.A metal CMP process removes copper and tantalum

    36、barrier layer Leave copper lines and plugs imbedded inside the dielectric layerHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm59PECVD NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGNitriden+Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm60PECVD USGP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSG

    37、USGNitriden+Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm61PECVD Etch Stop NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGNitriden+Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm62PECVD USGP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGn+USGHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/B

    38、ook.htm63Photoresist CoatingP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGn+USGPhotoresistHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm64Via 1 Mask Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm65Via 1 Mask Exposure and DevelopmentP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGn+USGPhotoresi

    39、stHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm66Etch USG,Stop on NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGn+PhotoresistUSGHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm67Strip PhotoresistP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGn+USGHong Xiao,Ph.D.www2.austin.cc.tx.us/Hong

    40、Xiao/Book.htm68Photoresist CoatingP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGn+USGPhotoresistHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm69Metal 1 MaskHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm70Metal 1 Mask Exposure and DevelopmentP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGUSGn+USG

    41、PhotoresistHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm71Etch USG and NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGn+PhotoresistUSGUSGHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm72Strip PhotoresistP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGn+USGUSGHong Xiao,Ph.D.www2.austin.cc.tx.us

    42、/HongXiao/Book.htm73Deposit Tantalum Barrier LayerP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGn+USGUSGHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm74Deposit CopperP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGn+USGUSGCopperHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm75CMP Copper and TantalumP

    43、-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGn+USGUSGCuM1Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm76PECVD Seal NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+USGWPSGn+USGUSGCuM1Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm77CMP Hardware Polishing pad Wafer carrier Slurry dispenserHong Xiao,Ph

    44、.D.www2.austin.cc.tx.us/HongXiao/Book.htm78Chemical Mechanical PolishingSlurryPolishing PadPressureWafer HolderWaferMembranePlatenSlurry DispenserRetaining Ring Hong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm79Linear Polishing SystemSlurryPressureWafer CarrierWaferMembraneSlurry DispenserRetai

    45、ning RingPad ConditionerBelt and Polishing PadSupport Fluid BearingHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm80Orbital PolishingDown ForceSlurryWaferCarrier FilmwcOrbital Motion,wpPolish PadHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm81Polishing Pad Porous,flexible polymer materi

    46、al cast,sliced polyurethane or urethane coated polyester felt Pad directly affects quality of CMP process Pad materials:durable,reproducible,compressible at process temperature Process requirement:high topography selectivity to achieve surface planarizationHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXia

    47、o/Book.htm82Polishing Pad Hardness Harder polishing pad:higher removal rate and better within die(WID)uniformity Softer pad:better within wafer(WIW)uniformity.Hard pads easier to cause scratches.The hardness is controlled by pad chemical compositions or by cellular structure.Hong Xiao,Ph.D.www2.aust

    48、in.cc.tx.us/HongXiao/Book.htm83Polishing Pad Cells absorb polishing slurry Filler improve mechanical properties Polishing pad surface roughness determines the conformality range.Smoother pad has poorer topographical selectivity less planarization effect.Rougher pad has longer conformality range and

    49、better planarization polishing resultHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm84Hard Rough PadPolishing PadFilmWaferPad MovementHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm85Soft Smooth PadPolishing PadFilmWaferPad MovementHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm86P

    50、ad Conditioning Pad becomes smoother due to the polishing Need to recreate rough pad surface In-situ pad conditioner for each pad The conditioner resurfaces the pad Removes the used slurry Supplies the surface with fresh slurryHong Xiao,Ph.D.www2.austin.cc.tx.us/HongXiao/Book.htm87Polishing Pad and

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