静态时序分析与设计验证教案课件.pptx

1、静态时序分析与设计验证静态时序分析与设计验证第1页/共78页第2页/共78页第3页/共78页第4页/共78页第5页/共78页第6页/共78页第7页/共78页第8页/共78页第9页/共78页第10页/共78页第11页/共78页第12页/共78页第13页/共78页第14页/共78页INCLKOUTEvery path has a start point and an end point:Start Points:End Points:只分析四种类型的时序路径 Input ports Clock pins Output ports Data input pins of sequential devi

2、cesD QclkD Qclkcombinational delays*第15页/共78页第16页/共78页Clock Period=Clock-to-Out+Data Delay+Setup Time-Clock Skew =tco+B+tsu-(E-C)fmax=1/Clock PeriodBCtcotsuE Clock Period第17页/共78页Data Delay(B)Source Register Clock Delay(C)Setup Time(tsu)BCtcotsuE Clock PeriodDestination Register Clock Delay(E)Clock

3、to Output(tco)10.384 ns+7.445 ns+0.180 ns-0.000 ns=124.86 MHzMessages Window(System Tab)in Quartus II第18页/共78页BCtcotsuE Clock PeriodECDataE-Cthtco+B 第19页/共78页Clock delaytsu thData delaytsu=data delay-clock delay+intrinsic tsuintrinsic tsu&holdth=clock delay-data delay+intrinsic th第20页/共78页AtcothChip

4、 AChip BBoard DelayInput DelaytSUACLKCLK第21页/共78页Data delaytcoClock delayclock delay+intrinsic tco+data delay=tcointrinsic tco第22页/共78页BtcotsuChip AChip BBoard DelaytcoACLKCLKtsuB第23页/共78页AtcotsuAltera DeviceExternal DeviceBoard DelaytsuA tCLK Input Maximum DelayInput Maximum DelaytsuACLKCLK第24页/共78

5、页AtcothAltera DeviceExternal DeviceBoard DelaythA Input Minimum DelayInput Minimum DelaythACLKCLK第25页/共78页BtcotsuAltera DeviceExternal DeviceBoard DelaytcoB tCLK-Output Maximum DelaytcoOutput Maximum DelayCLKCLK第26页/共78页BtcothAltera DeviceExternal DeviceBoard DelaytcoB Output Minimum DelaytcoOutput

6、Minimum DelayCLKCLK第27页/共78页第28页/共78页第29页/共78页第30页/共78页第31页/共78页Select Clock SetupWorst fmaxFmax Values Are Listed in Ascending Order;Worst Fmax Is Listed on the TopSource,Destination Registers&Associated Fmax Values第32页/共78页Highlight,Right-Click Mouse&Select List Pathsn进一步分析路径Similar Steps for All

7、Timing Path Analysis in Quartus II第33页/共78页Right-Click&Select LocateNotes:1)May Also Locate to Floorplan from Message Window 2)Use Similar Procedure for All Timing Path AnalysisCompilation Report第34页/共78页3.807 ns Is the Total Path Delay第35页/共78页Total delay:3.807 ns第36页/共78页Not Operational:Clock Skew

8、 Data DelayDiscover Internal Hold Time Issues before SimulationList Paths Window第37页/共78页Clock NameSelect ParameterPin Nametsu,tco,th Will All Show up in the Timing Analyzer ReportValueNote:Timing Analysis of tpd is similarRegister Name第38页/共78页第39页/共78页第40页/共78页第41页/共78页Slack=Largest Required Time-

9、Longest Actual TimeRequired Time=Clock Setup-tco-tsu+(clk-clk)Actual Time=Data Delaylaunch edgeclkclkcapturing edgeClock SetupclktcotsuCombinatorial LogicclkRegister 1Register 2data delay第42页/共78页launch edgeclkclkhold edgeClock HoldclktcothCombinatorial LogicclkRegister 1Register 2data delaySlack=Sh

10、ortest Actual Time-Smallest Required TimeActual Time=Data DelayRequired Time=Clock Hold-tco+th+(clk-clk)第43页/共78页fmax Timing AssignmentValues Are BLACK,Because Actual fmax Exceeds the Required fmaxtSU timing assignmentValues Are RED Because Actual tSU Falls below Required tSU第44页/共78页第45页/共78页For De

11、signs with Multiple Asynchronous Clocks,Enter Required Fmax for Each Individual ClockGlobal Clock Assignment for a Single Clock DesignAssignments Settings Timing Requirements&Options第46页/共78页第47页/共78页clk1tcotsuclk2capturing edgelaunching edgeclk1clk2dataRegister 1Register 2第48页/共78页Enter Name of Der

12、ived Clock SettingSelect Clock Setting on which This Derived Clock Is BasedClick on Derived Clock RequirementsClick New to Add New SettingEnter Name of Derived Clock Node第49页/共78页第50页/共78页第51页/共78页第52页/共78页第53页/共78页第54页/共78页Assignments Settings Simulator第55页/共78页第56页/共78页Enter End TimeRun Simulation

13、 until End of Stimulus FileSpecify Stimulus File第57页/共78页Reports Setup&Hold ViolationsMonitors&Reports Simulation for GlitchesReports Toggle RatioCompares Simulation Outputs to Outputs in Stimulus FileAutomatically Add Output Pins to SimulationGenerates Signal Activity File for PowerPlay Power Analy

14、zer第58页/共78页第59页/共78页第60页/共78页第61页/共78页Time BarSpecify Time BarSet Master Time Bar第62页/共78页Overwrite ValueToolbar ShortcutsHighlight Waveform第63页/共78页第64页/共78页第65页/共78页第66页/共78页第67页/共78页第68页/共78页View Simulation WaveformResult Waveform第69页/共78页第70页/共78页第71页/共78页Processing Simulation Debug BreakpointsClick on condition to Build Equation第72页/共78页Name BreakpointEnable/Disable BreakpointsArrange Order of Breakpoints第73页/共78页n Synopsys-VCS-VSS-Scirocco第74页/共78页Select Simulation ToolGenerate Power Input File第75页/共78页第76页/共78页第77页/共78页感谢您的观看。感谢您的观看。第78页/共78页