数字逻辑设计及应用-18课件.ppt

1、Chapter 7 Sequential Logic Design Chapter 7 Sequential Logic Design PrinciplesPrinciples(时序逻辑设计原理时序逻辑设计原理 )Latches and Flip-Flops (锁存器和触发器锁存器和触发器)Clocked Synchronous State-Machine Analysis (同步时序分析同步时序分析)Clocked Synchronous State-Machine Design (同步时序设计同步时序设计)Digital Logic Design and Application(数字逻辑设

2、计及应用数字逻辑设计及应用)1 1Review of Last Class(Review of Last Class(内容回顾内容回顾)时序逻辑电路时序逻辑电路输出取决于输入和过去状态输出取决于输入和过去状态电路特点：有反馈回路、有记忆元件电路特点：有反馈回路、有记忆元件双稳态元件双稳态元件QQ_L0态态 和和 1态态稳态稳态稳态稳态亚稳态亚稳态注意：亚稳态特性注意：亚稳态特性Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2 2时序逻辑电路时序逻辑电路输出取决于输入和过去状态输出取决于输入和过去状态电路特点：有反馈回路、有记忆元

3、件电路特点：有反馈回路、有记忆元件双稳态元件双稳态元件QQ_L0态态 和和 1态态如何加入控制信号？如何加入控制信号？QQLRSReview of Last Class(Review of Last Class(内容回顾内容回顾)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)3 3S S -R latchR latch（锁存器（锁存器）S_L=R_L=11 11 00 10 0S_L R_L维持原态维持原态0 11 0 1*1*Q QLS-R锁存器锁存器功能表功能表电路维持原态电路维持原态S_L=1,R_L=0Q=0,QL=1S

4、_L=0,R_L=1Q=1,QL=0S_L=R_L=0Q=QL=1，不定状态不定状态QQLS_LR_LSR清清0置置1不定不定S QR Q逻辑符号逻辑符号Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)4 4S-R Latch with EnableS-R Latch with Enable(具有使能端的具有使能端的S-RS-R锁存器锁存器)SRCQQLS_LR_L0 X X1 0 01 0 11 1 01 1 1C S R维持原态维持原态维持原态维持原态0 11 0 1*1*Q QL 功能表功能表(1).C=0时：时：维持原态维

5、持原态(2).C=1时：时：与与S-R锁存器相似锁存器相似注意：当注意：当S=R=1时，若时，若C由由10，则下一状态不可预测。则下一状态不可预测。逻逻 辑辑 符符 号号SCRQQ 又称又称“时钟时钟S-RS-R锁存器锁存器”Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)5 50 X X1 0 01 0 11 1 01 1 1C S R维持原态维持原态维持原态维持原态0 11 0 1*1*Q QL时钟时钟S-RS-R锁存器时序图锁存器时序图QSRC动作特点动作特点：输入信号在时钟：输入信号在时钟（使能端）有效期间，都能（使能端）

6、有效期间，都能直接改变触发器的状态。直接改变触发器的状态。Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)6 6D Latch(DD Latch(D锁存器锁存器)When D=1，Q=1C=0，QQLSRDC数据数据输入端输入端控制端控制端ENABLECLK输出状态保持不变输出状态保持不变输出随输入状态而改变输出随输入状态而改变C=1，When D=0，Q=0Q=DTransparent Latch(透明锁存器透明锁存器)C D Q QL1 0 0 11 1 1 00 X 保保 持持D锁存器锁存器功能表功能表D QC Q逻辑符号逻

7、辑符号Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)7 7Level-Sensitive D LatchLevel-Sensitive D LatchSR latch requires careful design to ensure SR=11 never occursD latch relieves designer of that burdenInserted inverter ensures R always opposite of SDQQCD latch symbolR1S1DCD latchQSR8 8Level-

8、Sensitive D LatchLevel-Sensitive D LatchR1S1DCD latchQSR10DCS1R1Q101010109 9特征方程：特征方程：Qn+1=D（C=1）01D=1D=0D=1D=001D01Qn+1状态转移真值表状态转移真值表Function Description of a D LatchFunction Description of a D Latch(D(D锁存器的功能描述锁存器的功能描述)状态图状态图Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1010tpw(min)0 00

9、11 01 1S R维持原态维持原态0 11 0 0*0*Q QLSRQtpLH(SQ)tpHL(RQ)SRQQL传播传播延迟延迟最小最小脉冲脉冲宽度宽度Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)Figure 7-811 11QDCtpLH(CQ)tpHL(DQ)tpLH(DQ)tpHL(CQ)在在C C的下降沿附近有一个的下降沿附近有一个时间窗时间窗这段时间内这段时间内D D输入一定不能变化输入一定不能变化tsetupSetup Time(建立时间建立时间)tholdHold Time(保持时间保持时间)Timing Pa

10、rameters for a D LatchTiming Parameters for a D Latch(D(D锁存器的时序图锁存器的时序图)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1212D Latch with CMOS Transmission GateD Latch with CMOS Transmission Gate(利用利用CMOSCMOS传输门的传输门的D D锁存器锁存器)QLQTGTGDCENEN_LABCMOSCMOS传输门传输门TGDigital Logic Design and Applicati

11、on(数字逻辑设计及应用数字逻辑设计及应用)1313QLQTG1TG2DCC=0 TG1 断开断开 TG2 连通连通保持原态保持原态Q_LQDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)D Latch with CMOS Transmission GateD Latch with CMOS Transmission Gate(利用利用CMOSCMOS传输门的传输门的D D锁存器锁存器)1414QLQTG1TG2DCC=1 TG1 连通连通 TG2 断开断开 QL=D Q=DC D Q QL1 0 0 11 1 1 00 X 保保

12、 持持功能表功能表Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)D Latch with CMOS Transmission GateD Latch with CMOS Transmission Gate(利用利用CMOSCMOS传输门的传输门的D D锁存器锁存器)1515D QC QD QC QD QC QD QC QDIN3:0 WRDOUT3:0RDApplicationsApplicationsof Latchesof Latches(锁存器的应用锁存器的应用)Digital Logic Design and Appli

13、cation(数字逻辑设计及应用数字逻辑设计及应用)1616Q DQ CXYCISiCi+1XiYiCiSCOCLK暂存暂存X YCI COSCi+1SiXi YiCi时钟控制时钟控制串行输入、串行输出串行输入、串行输出注意：注意：时钟同步时钟同步再谈串行输入再谈串行输入加法器的实现加法器的实现ApplicationsApplicationsof Latchesof Latches(锁存器的应用锁存器的应用)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1717Storing One Bit Storing One Bit Ex

14、ample Requiring Bit StorageExample Requiring Bit StorageFlight attendant call buttonPress call:light turns onStays on after button releaseda3.2BitStorageBlue lightCallbuttonCancelbutton1.Call button pressed light turns onBitStorageBlue lightCallbuttonCancelbutton2.Call button released light stays on

15、11181819Storing One Bit Storing One Bit Flip-Flops Flip-FlopsExample Requiring Bit StorageExample Requiring Bit StoragePress cancel:light turns offStays off after button releasedLogic gate circuit to implement this?QCallCancelDoesnt work.Q=1 when Call=1,but doesnt stay 1 when Call returns to 0Need s

16、ome form of“feedback”in the circuit3.2BitStorageBlue lightCallbuttonCancelbutton3.Cancel button pressed light turns off0191920First attempt at Bit StorageFirst attempt at Bit StorageNeed some sort of feedbackDoes circuit below do what we want?QSt2020First attempt at Bit StorageFirst attempt at Bit S

17、torageNo:Once Q becomes 1(when S=1),Q stays 1 forever no value of S can bring Q back to 0101010QtS0t1QS00t1QS11t1QS11t0QS10t0QS02121Bit Storage Using an SR LatchBit Storage Using an SR LatchQS(set)SR latchR(reset)Does the circuit to the right,with cross-coupled NOR gates,do what we want?Yes!How did

18、someone come up with that circuit?Maybe just trial and error,a bit of insight.2222Bit Storage Using an SR LatchBit Storage Using an SR Latch001R=1S=0tQ1010RS10t10Q100101tQS=0R=0 t QS=1R=0011 t QR=0S=010100011X0Recall NOR232324Example Using SR Latch for Bit Example Using SR Latch for Bit StorageStora

19、geSR latch can serve as bit storage in previous example of flight-attendant call buttonCall=1:sets Q to 1Q stays 1 even after Call=0Cancel=1:resets Q to 0BitStorageBlue lightCallbuttonCancelbutton242425Example Using SR Latch for Bit Example Using SR Latch for Bit StorageStorageBut,theres a problem.R

20、SQCallbuttonBlue lightCancelbutton101252526Problem with SR LatchProblem with SR LatchProblemIf S=1 and R=1 simultaneously,we dont know what value Q will takeR=1S=10000tQR=0S=00011tQR=0S=01100tQ01010101SRQt262627Problem with SR LatchProblem with SR LatchProblemIf S=1 and R=1 simultaneously,we dont kn

21、ow what value Q will take1t01Q0Q may oscillate.Then,because one path will be slightly longer than the other,Q will eventually settle to 1 or 0 but we dont know which.Known as a race condition.2727Problem with SR LatchProblem with SR LatchDesigner might try to avoid problem using external circuitCirc

22、uit should prevent SR from ever being 11But 11 can occur due to different path delaysRCnclCallSSR latchQCallbuttonCancelbuttonExternal circuit2828Problem with SR LatchProblem with SR LatchAssume 1 ns delay per gate.The longer path from Call to R than from Call to S causes SR=11 for short time could

23、be long enough to cause oscillation10101010CallCnclSRSR=112 ns2929Problem with SR LatchProblem with SR LatchGlitch can also cause undesired set or resetRCnclCallSSR latchQCallbuttonCancelbuttonExternal circuitSuppose this wire has 4 ns delay3030Problem with SR LatchProblem with SR Latch10101010CallC

24、nclSRSR=01(undesiredglitch)4 ns3131Solution:Level-Sensitive SR LatchSolution:Level-Sensitive SR LatchAdd enable input“C”Only let S and R change when C=0Ensure circuit in front of SR never sets SR=11,except briefly due to path delaysSet C=1 after time for S and R to be stableWhen C becomes 1,the stab

25、le S and R value passes through the two AND gates to the SR latchs S1 R1 inputs.R1S1SCRLevel-sensitive SR latchQSCQQRLevel-sensitive SR latch symbol3232Solution:Level-Sensitive SR LatchSolution:Level-Sensitive SR LatchR1S1SCallCnclCClkRLevel-sensitive SR latchQGlitch on R(or S)doesnt affect R1(or(S1

26、)0101S1R1CorrectValues whenenabled10101010CallCnclSR10C3333Flip-Flops(Flip-Flops(触发器触发器)Change its outputs only at the Rising or Falling Edge of a controlling CLK signal.(只在时钟信号的边沿改变其输出状态只在时钟信号的边沿改变其输出状态)CLKPositive-EdgeRising-Edge(正正边沿边沿上升沿上升沿)Negative-EdgeFalling-Edge(负边沿负边沿下降沿下降沿)Digital Logic De

27、sign and Application(数字逻辑设计及应用数字逻辑设计及应用)3434Flip-Flops(Flip-Flops(触发器触发器)从功能上分从功能上分D触发器、触发器、S-R触发器、触发器、J-K触发器、触发器、T触发器触发器从结构上分从结构上分主从结构触发器、边沿触发器主从结构触发器、边沿触发器其他类型触发器其他类型触发器带使能端的触发器、扫描触发器带使能端的触发器、扫描触发器施密特触发器、单稳态触发器施密特触发器、单稳态触发器Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)3535D Flip-FlopD Fl

28、ip-FlopFlip-flop:Bit storage that stores on clock edgeOne design master-servantClk=0 master enabled,loads D,appears at Qm.Servant disabled.Clk=1 Master disabled,Qm stays same.Servant latch enabled,loads Qm,appears at Qs.Thus,value at D(and hence at Qm)when Clk changes from 0 to 1 gets stored into se

29、rvant 3636D Flip-FlopD Flip-FlopClkrising edgesNote:Hundreds of different flip-flop designs existD latchmasterD latchservantDDmDsCsQmQsQsQQ CmClkD flip-flopClkD/DmQm/DsCmCsQsCan we design bit storage that only stores a value on the rising edge of a clock signal?3737D Flip-FlopD Flip-FlopSolves probl

30、em of not knowing through how many latches a signal travels when C=1 In figure below,signal travels through exactly one flip-flop,for Clk_A or Clk_BWhy?Because on rising edge of Clk,all four flip-flops are loaded simultaneously then all four no longer pay attention to their input,until the next risi

31、ng edge.Doesnt matter how long Clk is 1.383839D Flip-FlopD Flip-FlopTwo latches inside each flip-flopD1 Q1D2Q2D3Q3D4Q4YClkClk_AClk_B113939D Flip-Flops(DD Flip-Flops(D触发器触发器)D QC QD QC QQQLDCLKCLK=0时，时，CLK=1时，时，主锁存器工作，接收输入信号主锁存器工作，接收输入信号 Qm=D从锁存器不工作，输出从锁存器不工作，输出 Q 保持不变保持不变主锁存器不工作，主锁存器不工作，Qm 保持不变保持不变从

32、锁存器工作，将从锁存器工作，将 Qm 传送到输出端传送到输出端Master(主主)Slave(从从)Qm 主从结构主从结构Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)4040DCLKQQmD QC QD QC QQQLDCLKQmDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)4141DCLKQD CLK Q QL0 0 11 1 0X 0 保保 持持X 1 保保 持持功功能能表表D Q CLK Q逻辑符号逻辑符号表示边沿触发特性表示边沿触发特性Digital L

33、ogic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)4242DCLKQDCLKQD D锁存器锁存器D D触发器触发器 边沿有效边沿有效电平有效电平有效Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)4343利用触发器作为移位寄存器（图利用触发器作为移位寄存器（图1 1）思考：能否将触发思考：能否将触发器改为锁存器器改为锁存器(图图2)2)DCLKQ1QD QC QD QC QQDCLKlatchlatch（图（图2 2）Q1D Q CLK QD Q CLK QQDCLKF/FF/F（图（图

34、1 1）Q1Applications of Flip-Flops Applications of Flip-Flops(触发器的应用触发器的应用)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)444445Problem with Level-Sensitive D LatchProblem with Level-Sensitive D LatchD latch still has problem(as does SR latch)When C=1,through how many latches will a signal tr

35、avel?Depends on how long C=14545Problem with Level-Sensitive D LatchProblem with Level-Sensitive D LatchClk_A signal may travel through multiple latchesClk_B signal may travel through fewer latches11?1?1?D1 Q1D2 Q2D3 Q3D4C4C3C2C1Q4YClkClk_AClk_B4646Problem with Level-Sensitive D LatchProblem with Le

36、vel-Sensitive D LatchR2S2D2C2D latchQ2D4C4Q4R1S1D1C1ClkD latchQ101010110011001(a)D3C3Q3014747Problem with Level-Sensitive D LatchProblem with Level-Sensitive D Latch(c)ClkD1Q1/D2S2R2Q2Short clockQ1 doesnt change(b)ClkD1Q1/D2S2R2Q22nd latch setLong clock4848Flight-Attendant Call Button Using D Flight

37、-Attendant Call Button Using D Flip-FlopFlip-FlopD flip-flop will store bitInputs are Call,Cancel,and present value of D flip-flop,QTruth table shown belowDQ QClkCallbuttonCancelbuttonBluelightComb.CircuitCallCnclQDL4949Flight-Attendant Call Button Using D Flight-Attendant Call Button Using D Flip-F

38、lopFlip-FlopPreserve value:if Q=0,make D=0;if Q=1,make D=1Cancel-make D=0Call-make D=1Lets give priority to Call-make D=1Circuit derived from truth table,using combinational logic design processDQQClkCallbuttonBluelightCallCancelQCancelbutton5050Timing Parameters for a D Flip-Flops Timing Parameters

39、 for a D Flip-Flops(D(D触发器的定时参数触发器的定时参数)Propagation Delay(传播延迟（传播延迟（CLKQ）)tpLH(CQ)tpHL(CQ)tsetup(建立时间建立时间)thold (保持时间保持时间)建立时间（输入信号先于时钟到达的时间）建立时间（输入信号先于时钟到达的时间）保持时间（有效时钟沿后输入信号保持的时间）保持时间（有效时钟沿后输入信号保持的时间）D CLKQDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)5151利用利用CMOS传输门实现传输门实现 主从结构主从结构Slave

40、(从触发器从触发器)Master(主触发器主触发器)回顾：利用回顾：利用COMSCOMS传输门的传输门的D D锁存器锁存器Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)5252Clock SignalClock SignalFlip-flop Clk inputs typically connect to one clock signalComing from an oscillator componentOsc.Clk535354Clock SignalClock SignalGenerates periodic pulsin

41、g signalBelow:Period=20 ns,Frequency=1/20 ns=50 MHzCycle is duration of 1 period(20 ns);below shows 3.5 cycles0 nsTime:Clk10 ns20 ns30 ns40 ns00001011150 ns60 nsPeriod/Freq shortcut:Remember 1 ns 1 GHz100 GHz10 GHz1 GHz100 MHz10 MHz0.01 ns0.1 ns1 ns10 ns100 nsPeriodFreq.5454第第7 7章作业章作业7.4(7.2)7.5(7.

42、3)7.7(7.5)7.12(7.9)7.13(7.10)7.16(7.13)7.17(7.14)7.18(7.15)7.19(7.16)7.20(7.19)7.21(7.20)(c)7.41(7.27)7.43(7.28)7.46(7.34)7.51(7.47)7.52(7.49)7.77(7.68)5555Draw the Output Waveform of the D Flip-FlopDraw the Output Waveform of the D Flip-FlopDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)A Class Problem (A Class Problem (每课一题每课一题 )DCLKQ5656