verilog-设计可综合状态机指导原则课件.ppt

1、图图1.时钟同步的状态机结构时钟同步的状态机结构(Mealy 状态机状态机)下一状态下一状态的逻辑的逻辑 F F输出逻辑输出逻辑 G G状态状态寄存器寄存器 clk 输入Moor Moor 状态机状态机下一个状态下一个状态 =F(=F(当前状态，输入信号当前状态，输入信号)输出信号输出信号 =G(=G(当前状态当前状态)；下一状下一状态的逻态的逻辑辑 F F输出逻辑输出逻辑 G G状态状态寄存器寄存器图2.时钟同步的状态机结构(Moor状态机)有限状态机的图形表示有限状态机的图形表示 图形表示：状态、转移、条件和逻辑开关图形表示：状态、转移、条件和逻辑开关图图3.4 3.4 状态转移图状态转移

2、图Idle Start Stop Clear A/K1=0!A A/K2=1!Reset/K2=0 K1=0!Reset/K2=0 K1=0（!Reset|!A）/K2=0 K1=1!Reset/K2=0 K1=01.定义模块名和输入输出端口；定义模块名和输入输出端口；2.定义输入、输出变量或寄存器；定义输入、输出变量或寄存器；3.定义时钟和复位信号；定义时钟和复位信号；4.定义状态变量和状态寄存器；定义状态变量和状态寄存器；5.用时钟沿触发的用时钟沿触发的always块表示状态转移过程；块表示状态转移过程；6.在复位信号有效时给状态寄存器赋初始值；在复位信号有效时给状态寄存器赋初始值；7.描

3、述状态的转换过程：符合条件，从一个状态到描述状态的转换过程：符合条件，从一个状态到另外一个状态，否则留在原状态；另外一个状态，否则留在原状态；8.验证状态转移的正确性，必须完整和全面。验证状态转移的正确性，必须完整和全面。ClockResetAK2K1input Clock,Reset A;output K2,K1;信号说明，引脚信号说明，引脚变量和常量变量和常量图图1.时钟同步的状态机结构时钟同步的状态机结构(Mealy 状态机状态机)下一状态下一状态的逻辑的逻辑 F F输出逻辑输出逻辑 G G状态状态寄存器寄存器 clk 输入信号变量、常量声明 每一个时钟沿产生一次可能的状态变化 stat

4、e 产生下一状态的组合逻辑 nextstate 产生输出K1的组合逻辑ResetAclkStopClear010010always20always30K10K20ClockResetAK2K1statemodule mux2(clk,ina,out);input clk,ina;output out;reg out;reg 1:0 state;parameter s0=2b00,s1=2b01,s2=2b10,s3=2b11;always (posedge clk)beginstate=s0;out=0;case(state)s0:begin state=(ina=1)?s1:s0;out=0

5、;ends1:begin state=(ina=1)?s2:s0;out=0;ends2:begin state=(ina=1)?s3:s0;out=0;ends3:begin state=(ina=1)?s3:s0;out=1;end endcaseendendmodule just_launchedis_landedabort_missionall_systems_goclklaunch_shuttleland_shuttlestart_countdownstart_trip_metercntjust_launchedis_landedabort_mission/launch_shuttl

6、e=1/land_shuttle=1/start_trip_meter=1HOLDSEQUENCELANDLAUNCHON_MISSIONcnt=0/start_countdown=1all_systems_gomodule statemachine(launch_shuttle,land_shuttle,start_countdown,start_trip_meter,clk,all_systems_go,just_launched,is_landed,cnt,abort_mission);output launch_shuttle,land_shuttle,start_countdown；

7、output start_trip_meter;input clk,just_launched,is_landed,abort_mission,all_systems_go;input 3:0 cnt;reg launch_shuttle,land_shuttle,start_countdown,start_trip_meter;/设置独热码状态的参数 parameter HOLD=5b00001,SEQUENCE=5b00010,LAUNCH=5b00100,ON_MISSION=5b01000，LAND=5b10000;reg 4:0 state;always(negedge clk or

8、 posedge abort_mission)begin /检查异步reset的值,即abort_mission的值 if(abort_mission)launch_shuttle,land_shuttle,start_trip_meter,start_countdown=4b0000;state=LAND;else begin/*主状态机，状态变量state*/case(state)HOLD:if(all_systems_go)begin state=SEQUENCE;start_countdown=1;end else state=HOLD;SEQUENCE:if(cnt=0)state=

9、LAUNCH;else state=SEQUENCE;LAUNCH:begin state=ON_MISSION;launch_shuttle=1;end ON_MISSION:/取消使命前，一直留在使命状态 if(just_launched)start_trip_meter=1;else state=ON_MISSION;LAND:if(is_landed)state=HOLD;else begin land_shuttle=1;state=LAND;end default:state=5bxxxxx;endcaseend end/end of alwaysendmoduleModule c

10、lk_3(clkin,reset,clkout);input clkin,reset;reg 1:0 state;reg clk1;always(posedge clkin or negedge reset)if(!reset)state=2b00;else case(state)2b00:state=2b01;2b01:state=2b11;2b11:state=2b00;default:state=2b00;endcasealways(negedge clk or negedge reset)if(!reset)clk1=1b0;elseclk1 y)begin tmp=x;x=y;y=t

11、mp;end endtaskendmodulemodule compare(equal,a,b);parameter size=1;output equal;input size-1:0 a,b;assign equal=（a=b）?1:0;endmodulemodule decoder(out,in);output 7:0 out;input 2:0 in;assign out=1b1in;/*把最低位的把最低位的1左移左移 in（根据从（根据从in口输入的值）口输入的值）位，并赋予位，并赋予out */endmodulemodule encoder1(none_on,out,in);out

12、put none_on;output 2:0 out;input 7:0 in;reg 2:0 out;reg none_on;always(in)begin:local /此处此处begin-end块必须有一模块名块必须有一模块名 integer i;out=0;none_on=1;/*returns the value of the highest bit number turned on*/for(i=0;i8;i=i+1)if(ini)begin out=i;none_on=0;end endendmodulemodule encoder2(none_on,out2,out1,out0

13、,h,g,f,e,d,c,b,a);input h,g,f,e,d,c,b,a;output none_on,out2,out1,out0;wire 3:0 outvec;assign outvec=h?4b0111:g?4b0110:f?4b0101:e?4b0100:d?4b0011:c?4b0010:b?4b0001:a?4b0000:4b1000;assign none_on=outvec3;assign out2=outvec2;assign out1=outvec1;assign out0=outvec0;endmodulemodule encoder3(none_on,out2,

14、out1,out0,h,g,f,e,d,c,b,a);input h,g,f,e,d,c,b,a;output out2,out1,out0，none_on;reg 3:0 outvec;assign none_on,out2,out1,out0=outvec;always(a or b or c or d or e or f or g or h)if(h)outvec=4b0111;else if(g)outvec=4b0110;else if(f)outvec=4b0101;else if(e)outvec=4b0100;else if(d)outvec=4b0011;else if(c)

15、outvec=4b0010;else if(b)outvec=4b0001;else if(a)outvec=4b0000;elseoutvec=4b1000;endmodulemodul emux1(out,a,b,sel);output out;input a,b,sel;assign out=sel?a:b;endmodule使用连续赋值、使用连续赋值、casecase语句或语句或if-elseif-else语句可以生成多路语句可以生成多路器电路，如果条件语句（器电路，如果条件语句（casecase或或if-elseif-else）中分支条件）中分支条件是互斥的话，综合器能自动地生成并行

16、的多路器。是互斥的话，综合器能自动地生成并行的多路器。module mux2(out,a,b,sel);output out;input a,b,sel;reg out;/用电平触发的用电平触发的always块来设计多路器的组合逻辑块来设计多路器的组合逻辑 always(a or b or sel)case(sel)1b1:out=a;1b0:out=b;default:out=bx;endcaseendmodulemodule mux3(out,a,b,sel);output out;input a,b,sel;reg out;always(a or b or sel)begin if(se

17、l)out=a;else out=b;endendmodulemodule parity(even_numbits,odd_numbits,input_bus);output even_numbits,odd_numbits;input 7:0 input_bus;assign odd_numbits=input_bus;assign even_numbits=odd_numbits;endmodule module trist1(out,in,enable);output out;input in,enable;assign out=enable?in:bz;endmodule module

18、 trist2(out,in,enable);output out;input in,enable;/bufif1是是 一个一个 Verilog门级原语（门级原语（primitive）bufif1 mybuf1(out,in,enable);endmodulemodule bidir(tri_inout,out,in,en,b);inout tri_inout;output out;input in,en,b;assign tri_inout=en?In:bz;assign out=tri_inout b;endmodulemodule dff(q,data,clk);output q;inp

19、ut data,clk;reg q;always(posedge clk)begin q=data;endendmodulemodule latch1(q,data,clk);output q;input data,clk;assign q=clk?data:q;endmodulemodule latch2(q,data,clk,set,reset);output q;input data,clk,set,reset;assign q=reset?0:(set?1:(clk?data:q);endmodulemodule latch3(q,data,clk);output q;input da

20、ta,clk;reg q;always(clk or data)if(clk)q=data;endmodulemodule shifter(din,clk,clr,dout);input din,clk,clr;output 7:0 dout;reg 7:0 dout;always(posedge clk)if(clr)/清零清零 dout=8b0;else begin dout =dout1;/左移一位左移一位 dout0=din;/把输入信号放入寄存器的最低位把输入信号放入寄存器的最低位 endendmodulemodule counter1(out,cout,data,load,cin,

21、clk);output 7:0 out;output cout;input 7:0 data;input load,cin,clk;reg 7:0 out;always(posedge clk)if(load)out=data;else out=out+cin;assign cout=(&out)&cin;/只有当只有当out7:0的所有各位都为的所有各位都为1/并且进位并且进位cin也为也为1时才能产生进位时才能产生进位coutendmodulemodule counter2(out,cout,data,load,cin,clk);output 7:0 out;output cout;inp

22、ut 7:0 data;input load,cin,clk;reg 7:0 out,preout;reg cout;always(posedge clk)out=preout;always(out or data or load or cin)begin cout,preout=out+cin;if(load)preout=data;endendmodulemodule dff2(q,qb,d,clk,set,reset);input d,clk,set,reset;output q,qb;reg q,qb;always(posedge clk or posedge reset)if(reset)begin q=0;qb=1;end else if(set)begin q=1;qb=0;end else begin q=d;qb=d;endendmodulemodule dff2(q,qb,d,clk,set,reset);input d,clk,set,reset;output q,qb;reg q,qb;always(posedge clk)if(reset)begin q=0;qb=1;end else if(set)begin q=1;qb=0;end else begin q=d;qb=d;endendmodule