SoC设计方法和实现第十一章-低功耗.ppt

1、SoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬第十一章第十一章 低功耗设计低功耗设计OutlineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the futureWhy Low PowerPotable system-Battery lifetimenExample:mobile phone,PDA,Digital cameraDesktops:high power consu

2、mptionnReliability and performancenNeed expensive chip package,cooling systemSeveral deleterious effectsnDecreased reliability and performancenIncreased cost:packaging cost and cooling systemnExceed power limits of the chip&systemPower,Cost and HeatComponent:silicon and packagenIncreased die size(wi

3、der power busses)nNeed better thermal capabilities(package material)nNeed better electrical capabilities System:Cooling and mechanicalsnLarger fansnOversized power suppliesPower limits to the walln1100W dc limit for 110V/20A plugChallenge of Design as Process ScalingOutlineWhy low powerSources of po

4、wer consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the futureSource of Power ConsumptionDynamic power consumptionStatic power consumptionKey areas of power consumption in SOCSource of Power Dissipation in CMOS DevicesC =node capacitancesNsw=switching ac

5、tivities (number of gate transitions per clock cycle)F =frequency of operationVDD =supply voltageQsc =charge carried byshort circuit currentper transitionIleak =leakage currentStatic Power Consumption:Leakage currents:nSub-threshold current(I2)nGate leakage nGate tunnelling(I4)nGate induced drain le

6、akage(I3)npn-junction reverse current(I1)DC currentsnAnalog circuit:sense-amps,pull-upsnState dependentLeakage vs.ProcessWhat will be the dominated leakage current?Long Channel(L1um)Very small leakageShort channel(L180nm,tox30A)Subthreshold leakageVery short channel(L90nm,tox20A)subthreshold+gate le

7、akageNano-scaled(L90nm,Tox20A)Subthreshold+gate+junction leakageSub-threshold leakage current Has become quite important with technology scalingGate leakage currentIs becoming important with shrinking device dimensions PN junction leakage currentNegligible OutlineWhy low powerSources of power consum

8、ptionLow power design methodologyLow power techniques Low power analysis and toolsTrends in the futureLow Power Design MethodologyMust know your systemMaximize the performance while minimize the power consumptionMinimize the power consumption while maximize the performanceOpportunities for Power Sav

9、ingOutlineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the futureLow Power TechniquesLeakage power controlDynamic power controlArchitecture level power optimizationSystem level power optimizationLow Power TechniquesProces

10、s scaling nLow Vdd,Multi-thresholdVoltage scalingnSubstrate bias(200mv)nMulti-voltage(voltage island)nDynamic voltage scaling;multi-thresholdHW design techniquesnPre-computation,glitch minimization,Logic level,Physical level optimizationLow power System/SW nPower aware Operation System,compiler,SW d

11、esign etc.Low Power Techniques on Chip DesignLeakage PowernMulti Vt optimizationnPower gatingnSubstrate biasnPower gatingDynamic PowernMulti-voltage designnAdvanced clock-gatingnGate-level power optimizationTechniques for Reduce Leakage PowerUsing Multi-Vt LibrariesTiming and leakage tradeoffnLow Vt

12、 cell:faster speed,high leakagenHigh Vt cell:slower speed,lower leakagenPrinciple:low Vt for critical path and high Vt for non-critical pathsHigh Vt cell on Critical PathHints:You need to have dual Vt library1.You need to pay for the extra layer mask for multi-vt Using Multi-Vt Libraries cont.Synthe

13、sis Strategy:nUse high Vt cells first,then fix setup violation by replace the high Vt cells on the critical path to low Vt cellsnUse low Vt cells first,then swap to high Vt cells,fix setup violation by swap low Vt cells on the pathsNo area penalty nLibrary design for freely mix and match on SoC desi

14、gnPower Gating Also called Multi-Threshold CMOS(MTCOMS),logic sleep control,etc.Active mode:sleep control devices on,VDDV and GNDV act as virtual supplySleep mode:sleep control devices off,reduce leakagenHigh Vt transistors reducing both leakage and switching powerPower Gating cont.Sleep transistors

15、 used only on the supply rail or on both supply and ground railsnNot added on every gatePower gating retention registernActive modenHigh performance regular FF functionnSleep ModenCut-off VddnLow leakage stage saving latch functionBody BiasVariable threshold according to body biasingZero body bias i

16、n active mode(Low Vt)Reverse body bias in stand-by mode(High Vt)Tradeoff between the time on module turn-on and leakage currentTriple well structure CMOS InverterHint:Do you have the triple well structuredstandard cell lib?Techniques for Reduce Dynamic PowerMulti Voltage DesignBlock based approach i

17、n the design flowNeed to additional isolation cells and voltage level-shifter cells between voltage domainsClock Gating Technology Toggling consume power.Enable the module clock only when neededgated_clkEnableLogicGlobalClkComb.LogicDataRegClock Gating Cell DesignProblem with simple clock gating:nUn

18、completed cyclenGlitchclk_enclkgclkClock Gating with Latchclk_enclkgclkAdd a transparent-low latchMake sure the clk gating cells are placed tightly for correct function clk cell hardeningCommonly in SoC:make a“hardmacro”-clk gating cellRTL code for clk cell:always(clk or clk_en)if(!clk)ctrl_latch=cl

19、k_en;assign gclk=ctrl_latch&clkClock gating cells and a glitch free clock gatingDQGLatchclk_enclkgclkClock Gating With Integrated Test LogicAbility to let clk pass through in test mode (TEST=1)Gated Clock in Clock Tree DesignDisable clocking near the root of a clock tree,instead of at each FF.Specia

20、l care must be taken in clk tree synthesis to prevent the buffers inserted between clk root and the clk gating cellGate Level OptimizationTechnology independent optimization:nCircuit optimization:logic optimization,reduce redundant logicnTrimming for low power:reduce positive slacknGate resizingnPin

21、 swapping/reassignmentnRe-mappingnPhase assignmentnRe-factoringLow power driven technology mappingnlow power cellGate Level Optimization Gate SizingGate sizingnDown-size gates on fast paths to decrease their input capacitances for minimizing switching current in front driver nEnlarge heavily loaded

22、gates to increase their output slew rates for minimizing short-circuit currentDealing with GlitchesFor some type of data path circuits,up to 60%of the dynamic power is due to glitchesVery expensive calculationnNeed to propagate probabilistic waveformsExample:Glitch MinimizationHazardous transition o

23、ccurs at the output of AND gate due to different delays through two different delay paths converging at the inputs to the gateAABBCdelay=1delay=2ABCAbufferdelay=1AABBCdelay=1delay=2ABCAPhysical Level OptimizationLibrary Design:Energy-efficient cells Design planning:develop a realizable floorplan and

24、 realistic budgets for powerPlacement and routing:reduce glitchesIn placement optimization:buffer&wire resizing Transistor resizing:minimize capacitanceWidth/Spacing/Shielding/Metal layer optimization to reduce C&R.Reduce via resistance by adding more viasPhysical level optimization cont.Power plann

25、ing:defines power rings and mesh.nPower driven floor-planningDecoupling cap between Supply and GroundnSudden change in power consumption occur when blocks are powered on or offnDecoupling capacitor helps to reduce the transient current for high speed designnHave seen in filler cell at 0.13um process

26、nBut the leakage on decoupling cap itself at 90nm and below must take into accountGlobal Clock RoutingReduce Clock LoadnReduce oversized clock drivernReduce#of clock driversnReduce#of clock tracksMinimum Width Clock Tracks are resistance limitednLower R for drivabilitynLower C for powernIncrease wid

27、th&space to minimize C&R where possible.nAdd enough vias to reduce resistanceArchitecture level Power OptimizationMemory OptimizationParallel/Pipeline AlgorithmMemory OptimizationMemory cell redesignnReduce leakagenDual Vt SRAM CellnGated Vdd SRAM cellnGated GND SRAM cellnPower-aware DRAMMemory hier

28、archynSmall segmentnEach bank can independently put into appropriate power modeMemory management&data localitynCachenMultiple power statesBank 1Bank 2.Bank 0activewaitPowerdown.System Level Power OptimizationEnergy is consumed by all hardware unitsSoftware organization affects hardware energy consum

29、ptionManagement:run-time system management and control of all unitsEnergy Saving PrincipleOnly need to run just fast enough to meet the application software deadlines and maintain qualitynRun task as slow as possiblenReduce voltage to lower levelnRun task in time availablenReduce voltage to match ti

30、meSource:ARM.IEM:Intellectual Energy ManagementDynamic power managementWhat is Dynamic power management?nTo selective shutoff or slow-down of system components that are idle or underutilizednPower manager observes system&responds at run-timeWRRService Queue(SQ)Service Provider(SP)Linux Online!h ht t

31、t tp p:w ww ww w.l li in nu ux x.o or rg gCommandsPower Management(PM)A AR RMMService Requestor(SR)Why OS Directed Power Management?PowerSavingWork SleepDeepSleepOffProgram 1Program 2Program 3Application Program InterfaceKernelDevice DriversI/OCPUHard DiskOSControl Systemresources.It can alsocontrol

32、 the power statesof the resourcesACPI(Advanced Configuration andPower Interface)provides and interfacebetween the OS andsystem resourcesSystem ResourcesACPI-Power Saving ModesPower ConsumptionNeed to developpower managementpoliciesDynamic Voltage and Frequency ScalingDynamic Power ManagementnChange

33、the power state of the system components to lower the energy consumption depending on the performance constraintsDynamic Voltage and Frequency Scaling(DVFS)nAdjust the performance and energy consumption levels while the device is activenKey is to meet users performance needs while saving energynRedu

34、ce the processors voltage and frequency to obtain quadric energy savingExample A close loop intelligent energy managementIncrease the battery life of handheld portable devices in several stages from 25%up to 400%.DVS&DFS designed by ARM&National Semiconductor ARM&National SemiconductorNews on July 1

35、8,2019:TSMC and ARM Collaboration Achieves Significant Power Reduction On 65nm Low-Power Test ChipPower Management StrategynMulti-corner timing closure capability,which anticipates the timing impact of voltage scaling on the timing of library cells that offer different threshold voltages.This techni

36、que recognizes shifts in the critical path and earmarks them for timing analysis at any point in the design cycle.nMulti-threshold(MT)CMOS technology is implemented together with dynamic voltage and frequency scaling(DVFS)to reduce dynamic and standby(leakage)power for different operating conditions

37、.nDesign methodologies are demonstrated for power-gating cell wake-up/sleep control,power isolation and timing signoff for voltage islands.nARM Intelligent Energy Manager(IEM)technology supports dynamic voltage and frequency scaling,and is now being extended to include leakage control using power ga

38、ting and state retention under software control.Summary of Power Reduction TechniqueSource:conference papers,magazine articles低功耗技术漏电功耗的减小静态功耗的减小时序影响面积影响设计方法影响验证复杂度影响仿真影响面积优化10%10%0%-10%无低无多阈值工艺80%0%0%2%低低无时钟门控020%0%2%低低无多电压50%40-50%0%10%中中低电源门控90-98%0%4-8%5-15%中高低动态电压及动态频率缩放 50-70%40-70%0%10%高高高Out

39、lineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the futurePurposeFind the main power consumption components in our design to help us optimization designFind the power consumption in early stage to to enable efficient des

40、ign space exploration and help system level decisions Power Types and UsesPeak powernNeed to size power busses,limit ground noise(bounce)Time averaged powernPackage choicesnCooling devices and systemnBattery lifeRMS(Root mean square)nUsed for electromigration rulesAccuracy vs.Efficiency TradeoffPowe

41、r Estimation and SimulationRTLnEarly-analysis,fastest,simulation pattern refining and debugging easiernLess accurate,results depend on the accuracy of library data Gate LevelnAccurate-analysis,simulation with RC and SDFnNeed accuracy library,state dependent leakage power not accurately modeled in li

42、brariesTransistor levelnVery accurate analysis,accurate leakage measurements.Results dont depend on library,close to silicon measurements,nVery late in design phase,long run timeGlance at ToolsAnalysis levelAnalysis ToolNotesRTLPowerTheater Power Complier(synthesis)Quick RTL power analysis;Power-awa

43、re synthesis and gate level optimizationGatePrimePower(simulation)Accurate dynamic power analysis,pattern-dependent modeling of captive switching,short-circuit&static powerTransistorPowerMill(simulation)Transistor-level,pattern dependant,high speed,high capacity simulation,with 25%of SPICEPolygonRai

44、lMillAstro-RailBlaster-Railvoltage drop and electromigration analysis on power and ground networkTrends in FutureDesign abstract level:nMore attention will be paid for the higher abstract level power modelLow power design for test circuits:nPower dissipation under testing condition is 100200%higher

45、than normalnTest scheduling;circuit;ATPG with less switching activity etc.Asynchronous circuits:nSynchronous circuit:Clock tree is power hungrynAsynchronous circuit:no need to balance clockMemory:nMemory will occupy more space in chip than Logic,that means memory system are required to perform power reductionSoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬Thank you