数字设计课件-第6章-组合逻辑设计实践2.ppt
- 【下载声明】
1. 本站全部试题类文档,若标题没写含答案,则无答案;标题注明含答案的文档,主观题也可能无答案。请谨慎下单,一旦售出,不予退换。
2. 本站全部PPT文档均不含视频和音频,PPT中出现的音频或视频标识(或文字)仅表示流程,实际无音频或视频文件。请谨慎下单,一旦售出,不予退换。
3. 本页资料《数字设计课件-第6章-组合逻辑设计实践2.ppt》由用户(三亚风情)主动上传,其收益全归该用户。163文库仅提供信息存储空间,仅对该用户上传内容的表现方式做保护处理,对上传内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知163文库(点击联系客服),我们立即给予删除!
4. 请根据预览情况,自愿下载本文。本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。
5. 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007及以上版本和PDF阅读器,压缩文件请下载最新的WinRAR软件解压。
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 数字 设计 课件 组合 逻辑设计 实践
- 资源描述:
-
1、22.7.211Chapter 6 Combinational Logic Design PracticesMSI building blocks are the important element of combinational circuits.22.7.21chapter 62本章重点n具备一定功能的通用组合逻辑电路的设计方法及实例n掌握常用的MSI的使用方法及功能扩展n掌握译码器、MUX实现组合逻辑功能的方法n能分析、设计由MSI构建的电路22.7.21chapter 636.1 Documentation Standard1.Signal Names and Active Leve
2、lsMost signals(signal name)have active level.active high active lowNaming convention surffix“_L”attaching to signal name represent active low level.Like,EN_L、READY_L In logic relation,EN_L=EN,READY_L=READY。22.7.21chapter 642.Active levels for pinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversion bub
3、bleActive lowENENDinstartDoutflgstartDinDoutflgActive hign22.7.21chapter 65Exp2:EN=1(active high),data can be transferredEN=0(active low),data can be transferredENCLKEN_LCLK22.7.21chapter 663.bubble-to-bubble logic designMake the logic circuit easier to understand.Exp:Not matchNot matchABSELDATAABAS
4、ELDATAmatchmatch22.7.21chapter 676.3 Combinational PLDs1.Programmable logic arrays(PLA)two level“ANDOR”device.Can be programmed to realize any sum-of-products logic expression.An nm PLA with p product terms:ninputs moutputs pproduct terms22.7.21chapter 6843 with 6 product termsAND array22.7.21chapte
5、r 6922.7.21chapter 6102.Programmable Array Logic DevicesFixed OR array,programmable AND arrayBidirectional input/output pins,熔丝型,熔丝型PAL16L8,Output enable22.7.21chapter 6113.Generic Array Logic Devices(GAL)an innovation of the PAL;can be erased and reprogrammed;22.7.21chapter 6126.4 DecodernAn import
6、ant type of combinational circuit.input code wordenable inputOutput code word decodeer1-to-1mapping1-out-of-m codenmn-bitm-bit22.7.21chapter 6131、bianry decodersninput code:n-bitnoutput code:2n-bit 2-4 decoder(2-22)I1I0Y3Y2Y1Y0truth table:?:?Yi:?:?I1I0Y3 Y2 Y1 Y0000001010010100100111000Yi=miY0=I1I0Y
7、1=I1I0Y2=I1I0Y3=I1I02-4decoderOne input combination chooses an output port.22.7.21chapter 614n2-4 decoder with enable inputYi=EN miENI1I0Y3Y2Y1Y00 00001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4 decoder22.7.21chapter 615(2)74139,dual 2-4 decoderInput code:B(MSB)A(LSB)Also be called address input.O
8、utput code:Y3_LY0_LEN 22.7.21chapter 616(3)74138,3-8 decoderuEnable inputEN=G1G2A_LG2B_LuInput code:C(MSB)、)、B、AuOutput code:Y0_L Y7_LuYi_L=(ENmi)Y0_LY1_LY2_LY3_L Y4_L Y5_L Y6_L Y7_LG1G2A_LG2B_LEN22.7.21chapter 617ENmsblsb22.7.21chapter 6182、realizing combinational circuits with decodernreview:canon
9、ical sumnDecoder output:Yi_L=(ENmi)when EN=1,Yi_L=mi=Mi add an NAND gate to the decoders output.Exp:(1)F=AB(0、3)F=AB+ABEnable asserted22.7.21chapter 619(2)if a 3-bit number XYZ is odd number,then ODD output 1,else output 0.realize the function with decoder and gates.solution:F=?F=XYZ(1,3,5,7)22.7.21
10、chapter 620(3)F=XYZ(0、1、5)解:解:22.7.21chapter 6213.Cascading binary decodersnHow to construct a 4-16、5-32 decoder?use multiple 2-4 or 3-8 decoders to cascade.nPS.:confirm the number of decoders according to the input and output bits.only one chip works in each decoding operation.22.7.21chapter 622Exp
11、:a 4-16 decoderInputs:4-bit N3、N2、N1、N0。Outputs:16-bit DEC15_LDEC0_LNeed 2 3-8 decoders.Use the MSB of the inputs as chip-select bit.000000010111100010011111N3 N2 N1 N0N3 N2 N1 N022.7.21chapter 623Chip selecting22.7.21chapter 624nExp:4-bit prime-number detector.Realizing it with 74138 and some gates
12、.N3N2N1N0U174HC138D_6VY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U274HC138D_6VY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U374HC30D_6VR1 1kR21kVCC5VGNDGNDF22.7.21chapter 6254、7-segment decoderClassify of 7-seg displayer:in materials:LED(发光二极管)(发光二极管)LCD(液晶)(液晶)In working mode:common-cathode(共
13、阴极共阴极)common-anode(共阳极共阳极)afbcegddpabcdedpfggndgnd22.7.21chapter 626 7-segment decoder transform the input BCD code to 7-segment displaying code.devices:7446A、74LS47(驱动共阳)(驱动共阳)74LS48、74LS49(驱动共阴)(驱动共阴)00001001 are useful input codes.10101111 are unused BCD code.22.7.21chapter 627U1A5B1C2D4OA11OD8OE
14、6OF13OC9OB10OG12BI3U2A B C D E F GCKHGNDVCCR1R6R7R8R9R10 R1174LS4922.7.21chapter 6285、BCD decoder(二(二十进制译码器)十进制译码器)Inputs:BCDY0Y9BCD decoderOutput:1-out-of 10 code74HC4222.7.21chapter 6295.5 Encoder1、binary encoder inputs:1-out-of-2n codeI0I1Im(m=2n-1)output:n-bitY0Y1Yn-1binary encoder22.7.21chapter
15、 6308-3 encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:active high22.7.21chapter 631Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7 Each input port has its corresponding output code.22.7.21chapter 6322、Priority Encode
16、r if multiple inputs are asserted,how to deal with?solution:assign priority to each input from high to low.let I7 highest priority and decrease from I6 down to I0 A2,A1,A0encode output IDLEwhen no input is asserted,IDLE=122.7.21chapter 633inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE111100111000011010000110
17、0000001011000000101000000001001000000001000000000000000122.7.21chapter 634Logic expressions for priority encoderH7=I7H6=I6I7H5=I5I6I7H0=I0I1I2I3I4I5I6I7A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7IDLE=(I0+I1+I2+I3+I4+I5+I6+I7)=I0I1I2I3I4I5I6I7Expressions for each asserted input in the truth table of p
18、riority encoderOutput code expressions 22.7.21chapter 6353、74148 Priority Encoder EI_L:Enable Input.I7_LI0_L:encode input,I7_L has highest priority.A2_LA0_L:encode output GS_L:GS_L=0 when one or more of the request inputs are asserted.EO_L:enable output,EO_L=0 when all of the request inputs are nega
展开阅读全文