数字设计基础双语课件(第4章).ppt

1、 4.Flip-flops and counters 4.1 Sequential circuits 4.2 Memory design using gates 4.3 Flip-flops4.4 Registers4.5 Counters1 4.1 Sequential circuits 1.Concept of sequential circuitThe logic circuits whose outputs depend not only on the present logic input values but also on previous logic input and out

2、put values are called sequential circuits.Counter is a common example of sequential circuit.2 4.1 Sequential circuits（2）Asynchronous sequential circuitA sequential logic circuit that does not use a synchronizing clock signal is called asynchronous sequential circuit.2.Classification of sequential ci

3、rcuit（1）Synchronous sequential circuitA sequential logic circuit whose output changes are initiated by an input clock signal and in which the outputs change upon the required clock signal transition is called a synchronous sequential circuit.3 4.2 Memory design using gates A logic circuit can mainta

4、in a constant output value by the use of feedback whereby the output is connected to the inputs to reinforce the output value.Set-reset memory design )R=0,S=1,Q=0;)R=1,S=0,Q=1;From the circuit,we can get:Once the output has been forced to a 0 or a 1,the input can return to a 1 and the output will re

5、main unchanged.4 4.2 Memory design using gates It is often convenient to have both a true output Q and a complementary output Q which in normal operation of the memory circuit has the opposite logical value to Q.The memory design shown below is called a latch.The latch can store one binary value,but

6、 its outputs will change when one of the inputs changes to a 0.Disadvantage of latch:5 4.2 Memory design using gates Sometimes we have active high inputs memory design.6 4.3 Flip-flops Normally we want the output changes to be synchronized with a clock signal.Such memory designs are called flip-flop

7、s.A flip-flop can store a single bit by producing an output of a 0 or a 1 continuously until changed by conditions on the inputs and a clock signal transition.1.Flip-flopFlip-flops are the basic building block of sequential circuits.There are several types of flip-flops.7 4.3 Flip-flops 2.R-S flip-f

8、lopThe R-S flip-flop has two inputs,named S and R.S for set,R for reset.（1）Truth tableQ+indicates the value of Q after the activating clock transition.Q-is the value before the clock transition.However,only after a specified clock transition occurs will the outputs take on the required values,before

9、 which the outputs can not change even if the S or R inputs change.8 4.3 Flip-flops（2）Characteristic equationCharacteristic equation describes the relationship between the Q output and inputs.The characteristic equation of R-S flip-flop is:Q+=Q R+S（3）Level triggeringThe simplest form of clock activa

10、tion is level triggering.When the clock becomes a 1,the outputs assume their values according to the inputs.9 4.3 Flip-flops)When CP=1,the values on S and R enter the circuit and the outputs will assume the corresponding input values.)When CP=0,the outputs of gates G3 and G4 will be at a 1 irrespect

11、ive of the logic levels on S and R.Level triggered R-S flip-flop10 4.3 Flip-flops If we simply want to store the value of one binary digit,then D flip-flop is needed which has only one data input to specify a 0 or a 1 to be stored.3.D flip-flopThe Q output simply becomes the value on the D input aft

12、er the activating clock transition.11 4.3 Flip-flops（1）Characteristic equationQ+=DTruth table（3）Edge triggering（2）Truth tableThe output changes on a transition of the clock signal and the inputs are allowed to change at other times without affecting the output.This form of clock activation is called

13、 edge triggering.12 4.3 Flip-flops Master-slave flip-flopIn a master-slave flip-flop,two flip-flops are used in cascade.The first one,the master,captures the input values when clock is a 1.The second one,the slave,takes on the masters output on the falling edge of the clock.13 4.3 Flip-flops Though

14、the outputs of master-slave flip-flop will only change on the negative edge of the clock,its design still does not eliminate the constraint that the inputs cannot change while the clock is HIGH.Limitations of master-slave flip-flopsAlso the output is delayed until the falling edge of the clock signa

15、l.14 4.3 Flip-flops Edge-triggered flip-flopIn an edge-triggered flip-flop,only the transition from one specified logic level to the other logic level can cause the outputs to change.Only the value of inputs at the time of the clock transition determines the output value.There are two forms of edge

16、triggering:positive edge triggering and negative edge triggering.15 4.3 Flip-flops In positive edge triggering,the activating transition is from a logic 0 to a logic 1.In negative edge triggering,the activating transition is from a logic 1 to a logic 0.D-type flip-flop symbolsThe outputs will only c

17、hange on the specified transition of the clock.The change is determined by the value on D at that time.16 4.3 Flip-flops Asynchronous set and reset inputsD-type flip-flops with asynchronous set and reset inputsFlip-flops are provided with asynchronous set and reset inputs to set the output to a 1 an

18、d reset the output to a 0 immediately and not in synchronization with the clock.17 4.3 Flip-flops 4.J-K flip-flopOne of the most common requirements is to create a circuit whose outputs change from a 0 to a 1 or from a 1 to a 0,the so-called toggle action.The J-K flip-flop provides this toggle opera

19、tion in addition to being able to set or reset the flip-flop.JK-type flip-flop symbols18 4.3 Flip-flops（1）Truth table（2）Characteristic equationQ+=JQ-+KQ-A J-K flip-flop can emulate a D flip-flop by applying D to J and D to K using an inverter.19 4.3 Flip-flops 5.Finite state machineAll practical seq

20、uential circuits have a finite number of states,hence the term finite state machine is used for describing practical sequential circuits.Flip-flop State diagramA flip-flop can exist in one of two states:0 and 1.A state change will be initiated by a specified change of inputs and the activating clock

21、 transition.We can illustrate the states of a sequential circuit and the conditions for changing from one state to another in a state diagram.20 4.3 Flip-flops Flip-flop state diagram21 4.4 Registers 1.RegistersA flip-flop can store one binary digit.Often we want to store a group of binary digits a

22、binary word say 8 bits(a byte).To store eight bits,we can use eight flip-flops to form an 8-bit register.8-bit data register22 4.4 Registers 2.Shift registersIn a shift register,the outputs of each flip-flop pass onto the adjacent flip-flop by connecting the output of each flip-flop to the input of

23、the adjacent flip-flop.A single data input is applied to the first flip-flop,and successive clock transitions will cause the data to shift one place right.23 4.4 Registers The data is entered serially(one bit at a time)at one end and is read out in parallel(all bits together)from the flip-flops.8-bi

24、t serial-in parallel-out shift register(1)Serial-in parallel-out shift register24 4.4 Registers(2)Serial-in serial-out shift registerThe data is entered serially at one end and retrieved serially from the last flip-flop.8-bit serial-in serial-out shift register25 4.4 Registers(3)Parallel-in parallel

25、-out shift registerIt is simply a normal data register.8-bit parallel-in parallel-out shift register26 4.4 Registers 3.ApplicationsDivisionA register is often used to hold data,a set of bits that represents a binary number.A shift register can be used to divide the number by a power of 2 by simply s

26、hifting the number in the shift register the appropriate number of places right.MultiplicationA shift register can be used to multiply the number by a power of 2 by shifting the number in the shift register the appropriate number of places left.27 4.5 Counters 1.CountersA counter is a sequential cir

27、cuit that will create a specific recurring output sequence.Counters can be constructed with flip-flops with one flip-flop for each bit of the counting sequence.2.Classification of counters)binary-up counter)binary-down counter)bidirectional binary counter(1)According to the trend of output sequence 28