VHDL程序设计数字电子表2收集.ppt

1、6 个七段数码管个七段数码管SEGOUT(8)(8)CLR 时钟显示时钟显示电路方框图电路方框图CP FPGASELOUT(6)(6)24进进制制计数器计数器60进进制制计数器计数器60进进制制计数器计数器BCD 七段译码电路七段译码电路BCD 选择选择BCD(8)(8)BIN(6)(6)6 个七段数码管个七段数码管扫描电路扫描电路 S(3)(3)SEG(8)(8)NUM(4)(4)BCD(3-0)(3-0)BCD(7-4)(7-4)ENB(0)(0)ENB(1)(1)ENB(2)(2)DBHDBMDBSBIN(6)(6)时钟显示时钟显示电路方框图电路方框图SEC CLR CYH CYS CY

2、M 分频器分频器CP 38译译码码24进进制制计数器计数器60进进制制计数器计数器60进进制制计数器计数器BCD 七段译码电路七段译码电路BCD 选择选择BCD(8)(8)BIN(6)(6)6 个七段数码管个七段数码管扫描电路扫描电路 S(3)(3)SEG(8)(8)NUM(4)(4)BCD(3-0)(3-0)BCD(7-4)(7-4)ENB(0)(0)ENB(1)(1)ENB(2)(2)DBHDBMDBSBIN(6)(6)时钟显示时钟显示电路方框图电路方框图SEC CLR CYH CYS CYM 分频器分频器CP 38译译码码PROCESS(CP)PROCESS(CP)BeginBeginI

3、F CPEvent AND CP=1 thenIF CPEvent AND CP=1 thenDLY=Q(21)DLY=Q(21);Q=Q+1;Q=Q+1;END IF;END IF;END PROCESS;END PROCESS;Free_Counter:BlockFree_Counter:Block Signal Signal Q Q:STD_LOGIC_VECTOR(24 DOWNTO 0);:STD_LOGIC_VECTOR(24 DOWNTO 0);Signal DLY Signal DLY:STD_LOGIC;:STD_LOGIC;BeginBeginPROCESS(CP)PROC

4、ESS(CP)BeginBeginIF CPEvent AND CP=1 thenIF CPEvent AND CP=1 thenDLY=Q(21);DLY=Q(21);Q=Q+1;Q=Q+1;END IF;END IF;END PROCESS;END PROCESS;SEC=SEC=Q(21)AND NOT DLYQ(21)AND NOT DLY;-about 1Hz -about 1Hz S=Q(15 DOWNTO 13);S=Q(15 DOWNTO 13);-about 250 Hz-about 250 HzENB ENB=001 WHEN(S=0 OR S=1)ELSE=001 WHE

5、N(S=0 OR S=1)ELSE010 WHEN(S=2 OR S=3)ELSE010 WHEN(S=2 OR S=3)ELSE100 WHEN(S=4 OR S=5)ELSE100 WHEN(S=4 OR S=5)ELSE000;000;BIN BIN=DBS WHEN ENB=001 ELSE=DBS WHEN ENB=001 ELSEDBM WHEN ENB=010 ELSEDBM WHEN ENB=010 ELSEDBH WHEN ENB=100 ELSEDBH WHEN ENB=100 ELSE000000;000000;End Block Free_Counter;End Blo

6、ck Free_Counter;-主文件声明代码主文件声明代码COMPONENT COUNTER60COMPONENT COUNTER60PORT(PORT(CPCP:IN:IN STD_LOGIC;STD_LOGIC;BINBIN:OUT:OUTSTD_LOGIC_VECTOR(5 DOWNTO 0);STD_LOGIC_VECTOR(5 DOWNTO 0);S S:IN:IN STD_LOGIC;STD_LOGIC;CLRCLR:IN:IN STD_LOGIC;STD_LOGIC;ECEC:IN STD_LOGIC;:IN STD_LOGIC;CY60CY60:OUT STD_LOGIC:

7、OUT STD_LOGIC););END COMPONENT;END COMPONENT;-子文件定义代码子文件定义代码-*LIBRARY IEEE;LIBRARY IEEE;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY COUNTER60 ISENTITY COUNTER60 ISPORT(PORT(CP CP:IN STD_LOGIC;IN STD_LOGIC;BINBIN:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);OUT STD_LOGIC_VECTOR(5 DOW

8、NTO 0);S S :IN STD_LOGIC;IN STD_LOGIC;CLR CLR :IN STD_LOGIC;IN STD_LOGIC;EC EC :IN STD_LOGIC;IN STD_LOGIC;CY60 CY60:OUT STD_LOGICOUT STD_LOGIC););END COUNTER60;END COUNTER60;-子文件定义代码子文件定义代码ARCHITECTURE a OF ARCHITECTURE a OF COUNTER60COUNTER60 IS ISSIGNAL Q:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL Q:STD_

9、LOGIC_VECTOR(5 DOWNTO 0);SIGNAL RST,DLY:STD_LOGIC;SIGNAL RST,DLY:STD_LOGIC;BEGINBEGINPROCESS(CP,RST)PROCESS(CP,RST)BEGINBEGINIF RST=1 THENIF RST=1 THENQ=000000;Q=000000;ELSIF CPevent AND CP=1 THENELSIF CPevent AND CP=1 THENDLY=Q(5);DLY=Q(5);IF EC=1 THENIF EC=1 THENQ=Q+1;Q=Q+1;END IF;END IF;END IF;EN

10、D IF;END PROCESS;END PROCESS;CY60=CY60=NOT Q(5)AND DLY;NOT Q(5)AND DLY;RST=1 WHEN Q=60 OR CLR=1 ELSERST=1 WHEN Q=60 OR CLR=1 ELSE 0;0;BIN=BIN=Q Q WHEN S=1 ELSE WHEN S=1 ELSE 000000;000000;END a;END a;-主文件声明代码主文件声明代码COMPONENT COUNTER24COMPONENT COUNTER24PORT(PORT(CPCP:IN:IN STD_LOGIC;STD_LOGIC;BINBIN

11、:OUT:OUTSTD_LOGIC_VECTOR(5 DOWNTO 0);STD_LOGIC_VECTOR(5 DOWNTO 0);S S:IN:IN STD_LOGIC;STD_LOGIC;CLRCLR:IN:IN STD_LOGIC;STD_LOGIC;ECEC:IN STD_LOGIC;:IN STD_LOGIC;CY60CY60:OUT STD_LOGIC:OUT STD_LOGIC););END COMPONENT;END COMPONENT;-子文件定义代码子文件定义代码-*LIBRARY IEEE;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

12、USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY COUNTER24 ISENTITY COUNTER24 ISPORT(PORT(CP CP:IN STD_LOGIC;IN STD_LOGIC;BINBIN:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);OUT STD_LOGIC_VECTOR(5 DOWNTO 0);S S :IN STD_LOGIC;IN STD_LOGIC;CLR CLR :IN STD_LOGIC;

13、IN STD_LOGIC;EC EC :IN STD_LOGIC;IN STD_LOGIC;CY24 CY24:OUT STD_LOGICOUT STD_LOGIC););END COUNTER24;END COUNTER24;-子文件定义代码子文件定义代码ARCHITECTURE a OF COUNTER24 ISARCHITECTURE a OF COUNTER24 ISSIGNAL Q SIGNAL Q:STD_LOGIC_VECTOR(4 DOWNTO 0);STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL RST,DLY:SIGNAL RST,DLY:STD_L

14、OGIC;STD_LOGIC;BEGINBEGINPROCESS(CP,RST)PROCESS(CP,RST)BEGINBEGINIF RST=1 THENIF RST=1 THENQ=00000;Q=00000;ELSIF CPevent AND CP=1 THENELSIF CPevent AND CP=1 THENDLY=Q(4);DLY=Q(4);IF EC=1 THENIF EC=1 THENQ=Q+1;Q=Q+1;END IF;END IF;END IF;END IF;END PROCESS;END PROCESS;CY24=CY24=NOT Q(4)AND DLY;NOT Q(4

15、)AND DLY;RST=1 WHEN Q=24 OR CLR=1 ELSERST=1 WHEN Q=24 OR CLR=1 ELSE 0;0;BIN=BIN=(0&Q)(0&Q)WHEN S=1 ELSE WHEN S=1 ELSE 000000;000000;END a;END a;Binary_BCD:BlockBinary_BCD:BlockBEGINBEGINBCD=BCD=00000000 WHEN BIN=0 ELSE00000000 WHEN BIN=0 ELSE00000001 WHEN BIN=1 ELSE00000001 WHEN BIN=1 ELSE00000010 W

16、HEN BIN=2 ELSE00000010 WHEN BIN=2 ELSE00000011 WHEN BIN=3 ELSE00000011 WHEN BIN=3 ELSE00000100 WHEN BIN=4 ELSE00000100 WHEN BIN=4 ELSE00000101 WHEN BIN=5 ELSE00000101 WHEN BIN=5 ELSE00000110 WHEN BIN=6 ELSE00000110 WHEN BIN=6 ELSE00000111 WHEN BIN=7 ELSE00000111 WHEN BIN=7 ELSE00001000 WHEN BIN=8 EL

17、SE00001000 WHEN BIN=8 ELSE00001001 WHEN BIN=9 ELSE00001001 WHEN BIN=9 ELSE00010000 WHEN BIN=10 ELSE00010000 WHEN BIN=10 ELSE00010001 WHEN BIN=11 ELSE00010001 WHEN BIN=11 ELSE00010010 WHEN BIN=12 ELSE00010010 WHEN BIN=12 ELSE00010011 WHEN BIN=13 ELSE00010011 WHEN BIN=13 ELSE00010100 WHEN BIN=14 ELSE0

18、0010100 WHEN BIN=14 ELSE00010101 WHEN BIN=15 ELSE00010101 WHEN BIN=15 ELSE00010110 WHEN BIN=16 ELSE00010110 WHEN BIN=16 ELSE00010111 WHEN BIN=17 ELSE00010111 WHEN BIN=17 ELSE00011000 WHEN BIN=18 ELSE00011000 WHEN BIN=18 ELSE00011001 WHEN BIN=19 ELSE00011001 WHEN BIN=19 ELSE00100000 WHEN BIN=20 ELSE0

19、0100000 WHEN BIN=20 ELSE00100001 WHEN BIN=21 ELSE00100001 WHEN BIN=21 ELSE00100010 WHEN BIN=22 ELSE00100010 WHEN BIN=22 ELSE00100011 WHEN BIN=23 ELSE00100011 WHEN BIN=23 ELSE00100100 WHEN BIN=24 ELSE00100100 WHEN BIN=24 ELSE00100101 WHEN BIN=25 ELSE00100101 WHEN BIN=25 ELSE00100110 WHEN BIN=26 ELSE0

20、0100110 WHEN BIN=26 ELSE00100111 WHEN BIN=27 ELSE00100111 WHEN BIN=27 ELSE00101000 WHEN BIN=28 ELSE00101000 WHEN BIN=28 ELSE00101001 WHEN BIN=29 ELSE00101001 WHEN BIN=29 ELSE00110000 WHEN BIN=30 ELSE00110000 WHEN BIN=30 ELSE00110001 WHEN BIN=31 ELSE00110001 WHEN BIN=31 ELSE00110010 WHEN BIN=32 ELSE0

21、0110010 WHEN BIN=32 ELSE00110011 WHEN BIN=33 ELSE00110011 WHEN BIN=33 ELSE00110100 WHEN BIN=34 ELSE00110100 WHEN BIN=34 ELSE00110101 WHEN BIN=35 ELSE00110101 WHEN BIN=35 ELSE00110110 WHEN BIN=36 ELSE00110110 WHEN BIN=36 ELSE00110111 WHEN BIN=37 ELSE00110111 WHEN BIN=37 ELSE00111000 WHEN BIN=38 ELSE0

22、0111000 WHEN BIN=38 ELSE00111001 WHEN BIN=39 ELSE00111001 WHEN BIN=39 ELSE01000000 WHEN BIN=40 ELSE01000000 WHEN BIN=40 ELSE01000001 WHEN BIN=41 ELSE01000001 WHEN BIN=41 ELSE01000010 WHEN BIN=42 ELSE01000010 WHEN BIN=42 ELSE01000011 WHEN BIN=43 ELSE01000011 WHEN BIN=43 ELSE01000100 WHEN BIN=44 ELSE0

23、1000100 WHEN BIN=44 ELSE01000101 WHEN BIN=45 ELSE01000101 WHEN BIN=45 ELSE01000110 WHEN BIN=46 ELSE01000110 WHEN BIN=46 ELSE01000111 WHEN BIN=47 ELSE01000111 WHEN BIN=47 ELSE01001000 WHEN BIN=48 ELSE01001000 WHEN BIN=48 ELSE01001001 WHEN BIN=49 ELSE01001001 WHEN BIN=49 ELSE01010000 WHEN BIN=50 ELSE0

24、1010000 WHEN BIN=50 ELSE01010001 WHEN BIN=51 ELSE01010001 WHEN BIN=51 ELSE01010010 WHEN BIN=52 ELSE01010010 WHEN BIN=52 ELSE01010011 WHEN BIN=53 ELSE01010011 WHEN BIN=53 ELSE01010100 WHEN BIN=54 ELSE01010100 WHEN BIN=54 ELSE01010101 WHEN BIN=55 ELSE01010101 WHEN BIN=55 ELSE01010110 WHEN BIN=56 ELSE0

25、1010110 WHEN BIN=56 ELSE01010111 WHEN BIN=57 ELSE01010111 WHEN BIN=57 ELSE01011000 WHEN BIN=58 ELSE01011000 WHEN BIN=58 ELSE01011001 WHEN BIN=59 ELSE01011001 WHEN BIN=59 ELSE00000000;00000000;END Block Binary_BCD;END Block Binary_BCD;SELECT_BCD:BlockSELECT_BCD:BlockBEGINBEGINNUM=NUM=BCD(3 DOWNTO 0)B

26、CD(3 DOWNTO 0)WHEN(WHEN(S=0 OR S=2 OR S=4S=0 OR S=2 OR S=4)ELSE)ELSEBCD(7 DOWNTO 4);BCD(7 DOWNTO 4);End Block SELECT_BCD;End Block SELECT_BCD;SEVEN_SEGMENT:BlockSEVEN_SEGMENT:BlockBeginBegin -gfedcba -gfedcbaSEG=SEG=0111111 WHEN NUM=0 ELSE0111111 WHEN NUM=0 ELSE0000110 WHEN NUM=1 ELSE0000110 WHEN NU

27、M=1 ELSE 1011011 WHEN NUM=2 ELSE1011011 WHEN NUM=2 ELSE1001111 WHEN NUM=3 ELSE1001111 WHEN NUM=3 ELSE1100110 WHEN NUM=4 ELSE1100110 WHEN NUM=4 ELSE1101101 WHEN NUM=5 ELSE1101101 WHEN NUM=5 ELSE1111101 WHEN NUM=6 ELSE1111101 WHEN NUM=6 ELSE0000111 WHEN NUM=7 ELSE0000111 WHEN NUM=7 ELSE 1111111 WHEN N

28、UM=8 ELSE1111111 WHEN NUM=8 ELSE1101111 WHEN NUM=9 ELSE1101111 WHEN NUM=9 ELSE1110111 WHEN NUM=10 ELSE1110111 WHEN NUM=10 ELSE1111100 WHEN NUM=11 ELSE1111100 WHEN NUM=11 ELSE0111001 WHEN NUM=12 ELSE0111001 WHEN NUM=12 ELSE1011110 WHEN NUM=13 ELSE1011110 WHEN NUM=13 ELSE1111001 WHEN NUM=14 ELSE111100

29、1 WHEN NUM=14 ELSE1110001 WHEN NUM=15 ELSE1110001 WHEN NUM=15 ELSE0000000;0000000;End Block SEVEN_SEGMENT;End Block SEVEN_SEGMENT;CPINDCPQ#QDCPQ#QOUTl机械开关的抖动存在三种情况：按下时有抖动，松开时机械开关的抖动存在三种情况：按下时有抖动，松开时也有抖动；按下时有抖动，松开时无抖动；按下时无抖也有抖动；按下时有抖动，松开时无抖动；按下时无抖动，松开时有抖动。机械开关的抖动波形、抖动次数、动，松开时有抖动。机械开关的抖动波形、抖动次数、抖动时间都是

30、随机的，并不是每次都会产生抖动。抖动时间都是随机的，并不是每次都会产生抖动。l不同开关的最长抖动时间也不同。抖动时间的长短和机不同开关的最长抖动时间也不同。抖动时间的长短和机械开关特性有关，一般为械开关特性有关，一般为5ms到到10ms。但是，某些开关。但是，某些开关的抖动时间长达的抖动时间长达20ms，甚至更长。所以，在具体设计中，甚至更长。所以，在具体设计中要具体分析，根据实际情况来调整设计。要具体分析，根据实际情况来调整设计。l弹跳现象以及弹跳消除如图弹跳现象以及弹跳消除如图1 所示，虽然只是按下按键所示，虽然只是按下按键一次后放掉，结果在按键信号稳定先后竟出现了多个段一次后放掉，结果在

31、按键信号稳定先后竟出现了多个段脉冲，如果将这样的信号直接送到计数器之类的时序电脉冲，如果将这样的信号直接送到计数器之类的时序电路，结果将可能发生计数超过一次以上的误动作，从而路，结果将可能发生计数超过一次以上的误动作，从而误以为键盘按了多次。因此，必须加上弹跳消除电路，误以为键盘按了多次。因此，必须加上弹跳消除电路，除去短脉冲，避免误操作的发生。除去短脉冲，避免误操作的发生。l延时比较法或积分法延时比较法或积分法 比较法：这个方法很好理解，就是若干比较法：这个方法很好理解，就是若干个时钟周期读取的数据相同时我们认为个时钟周期读取的数据相同时我们认为收到了一个稳定的数据，否则认为是过收到了一个稳

32、定的数据，否则认为是过渡态。即采用若干位的移位寄存器，当渡态。即采用若干位的移位寄存器，当寄存器是全寄存器是全1或全或全0时才开始读数。这时才开始读数。这种方法的缺点是，当干扰脉冲较宽时我种方法的缺点是，当干扰脉冲较宽时我们必须等比地扩大移位寄存器的比特，们必须等比地扩大移位寄存器的比特，消耗较大资源。消耗较大资源。CPINDCPQ#QDCPQ#QSRQ#QDOUT-*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY Deb

33、unce isPORT(test_S:OUT STD_LOGIC;CP:IN STD_LOGIC;Key :IN STD_LOGIC;DLY_OUT :OUT STD_LOGIC;DIF_OUT:OUT STD_LOGIC);END Debunce;-*ARCHITECTURE a OF Debunce ISSIGNAL SAMPLE,DLY,NDLY,DIFF:STD_LOGIC;-Binary BEGINtest_S=SAMPLE;Free_Counter:Block-计数器计数器&产生扫描信号产生扫描信号 Signal Q:STD_LOGIC_VECTOR(14 DOWNTO 0);Si

34、gnal D0:STD_LOGIC;BeginPROCESS(CP)-计数器计数计数器计数 BeginIF CPEvent AND CP=1 thenD0=Q(4);Q=Q+1;END IF;END PROCESS;SAMPLE 25HZ脉冲脉冲-SAMPLE=Q(1)AND NOT D0;END Block Free_Counter;Debunce:Block-DebounceSIGNAL D0,D1,S,R:STD_LOGIC;BeginProcess(CP)BeginIF CPEVENT AND CP=1 THENIF SAMPLE=1 THEND1=D0;D0=KEY;-Two Sta

35、ge DelayS=D0 AND D1;-Generate S、RR=NOT D0 AND NOT D1;END IF;END IF;End Process;DLY=R NOR NDLY;-Debounce O/PNDLY=S NOR DLY;DLY_OUT=DLY;End Block Debunce;Differential:Block-DifferentialSignal D1,D0:STD_LOGIC;BEGINProcess(CP)BeginIF CPEVENT AND CP=1 THEND1=D0;D0=DLY;-Two State DelayEND IF;End Process;D

36、IFF=D0 AND NOT D1;-DifferentialEND Block Differential;DIF_OUT=DIFF;-Differential O/PEND a;时序图：时序图：CPINQ1Q2OUTCPINDCPQ#QDCPQ#QOUTCPINDCPQ#QDCPQ#QECCLKQLIBRARY IEEE;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTI

37、TY Timer_Dsp isENTITY Timer_Dsp isPORT(PORT(CP CP:IN STD_LOGIC;:IN STD_LOGIC;SEGOUT SEGOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);SELOUT SELOUT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);CLEAR CLEAR :IN STD_LOGIC:IN STD_LOGIC););END Timer_Dsp;END T

38、imer_Dsp;ARCHITECTURE a OF Timer_Dsp ISARCHITECTURE a OF Timer_Dsp ISCOMPONENT COUNTER60COMPONENT COUNTER60PORT(PORT(CPCP:IN:INSTD_LOGIC;STD_LOGIC;BINBIN:OUT:OUTSTD_LOGIC_VECTOR(5 DOWNTO 0);STD_LOGIC_VECTOR(5 DOWNTO 0);S S:IN:INSTD_LOGIC;STD_LOGIC;CLRCLR:IN:IN STD_LOGIC;STD_LOGIC;ECEC:IN STD_LOGIC;:

39、IN STD_LOGIC;CY60CY60:OUT STD_LOGIC:OUT STD_LOGIC););END COMPONENT;END COMPONENT;COMPONENT COUNTER24COMPONENT COUNTER24PORT(PORT(CPCP:IN:INSTD_LOGIC;STD_LOGIC;BINBIN:OUT:OUTSTD_LOGIC_VECTOR(5 DOWNTO 0);STD_LOGIC_VECTOR(5 DOWNTO 0);S S:IN:INSTD_LOGIC;STD_LOGIC;CLRCLR:IN:IN STD_LOGIC;STD_LOGIC;ECEC:IN

40、 STD_LOGIC;:IN STD_LOGIC;CY24CY24:OUT STD_LOGIC:OUT STD_LOGIC););END COMPONENT;END COMPONENT;SIGNAL BIN SIGNAL BIN:STD_LOGIC_VECTOR(5 DOWNTO 0);:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL DBS SIGNAL DBS:STD_LOGIC_VECTOR(5 DOWNTO 0);:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL DBM SIGNAL DBM:STD_LOGIC_VECTOR(5 DOWN

41、TO 0);:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL DBH SIGNAL DBH:STD_LOGIC_VECTOR(5 DOWNTO 0);:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL ENB SIGNAL ENB:STD_LOGIC_VECTOR(2 DOWNTO 0);:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL SECSIGNAL SEC:STD_LOGIC;:STD_LOGIC;SIGNAL BCD SIGNAL BCD:STD_LOGIC_VECTOR(7 DOWNTO 0);:STD_LOGI

42、C_VECTOR(7 DOWNTO 0);SIGNAL CLRSIGNAL CLR:STD_LOGIC;:STD_LOGIC;SIGNAL CYS,CYM,CYHSIGNAL CYS,CYM,CYH:STD_LOGIC;:STD_LOGIC;Signal S Signal S:STD_LOGIC_VECTOR(2 DOWNTO 0);:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL NUM SIGNAL NUM:STD_LOGIC_VECTOR(3 DOWNTO 0);:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SEGSIGNAL SEG:

43、STD_LOGIC_VECTOR(6 DOWNTO 0);:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGINBEGINConnection:BlockConnection:BlockBeginBeginU1:COUNTER60 PORT MAP(CP,DBS,ENB(0),CLR,SEC,CYS);U1:COUNTER60 PORT MAP(CP,DBS,ENB(0),CLR,SEC,CYS);U2:COUNTER60 PORT MAP(CP,DBM,ENB(1),CLR,CYS,CYM);U2:COUNTER60 PORT MAP(CP,DBM,ENB(1),CLR,CY

44、S,CYM);U3:COUNTER24 PORT MAP(CP,DBH,ENB(2),CLR,CYM,CYH);U3:COUNTER24 PORT MAP(CP,DBH,ENB(2),CLR,CYM,CYH);CLR=CLEAR;CLR=CLEAR;SELOUT=S;SELOUT=S;SEGOUT(6 DOWNTO 0)=SEG;SEGOUT(6 DOWNTO 0)=SEG;SEGOUT(7)=0;SEGOUT(7)=0;End Block Connection;End Block Connection;Free_Counter:BlockFree_Counter:Block Signal S

45、ignal Q Q:STD_LOGIC_VECTOR(24 DOWNTO 0);:STD_LOGIC_VECTOR(24 DOWNTO 0);Signal DLY Signal DLY:STD_LOGIC;:STD_LOGIC;BeginBeginPROCESS(CP)PROCESS(CP)-计数器计数计数器计数 BeginBeginIF CPEvent AND CP=1 thenIF CPEvent AND CP=1 thenDLY=Q(21);DLY=Q(21);Q=Q+1;Q=Q+1;END IF;END IF;END PROCESS;END PROCESS;SEC=Q(21)AND N

46、OT DLY;SEC=Q(21)AND NOT DLY;-about 1Hz -about 1Hz S=Q(15 DOWNTO 13);S=Q(15 DOWNTO 13);-about 250 Hz-about 250 HzENB=001 WHEN(S=0 OR S=1)ELSEENB=001 WHEN(S=0 OR S=1)ELSE010 WHEN(S=2 OR S=3)ELSE010 WHEN(S=2 OR S=3)ELSE100 WHEN(S=4 OR S=5)ELSE100 WHEN(S=4 OR S=5)ELSE000;000;BIN=DBS WHEN ENB=001 ELSEBIN

47、=DBS WHEN ENB=001 ELSEDBM WHEN ENB=010 ELSEDBM WHEN ENB=010 ELSEDBH WHEN ENB=100 ELSEDBH WHEN ENB=100 ELSE000000;000000;End Block Free_Counter;End Block Free_Counter;Binary_BCD:BlockBinary_BCD:BlockBEGINBEGINBCD=BCD=00000000 WHEN BIN=0 ELSE00000000 WHEN BIN=0 ELSE00000001 WHEN BIN=1 ELSE00000001 WHE

48、N BIN=1 ELSE00000010 WHEN BIN=2 ELSE00000010 WHEN BIN=2 ELSE00000011 WHEN BIN=3 ELSE00000011 WHEN BIN=3 ELSE00000100 WHEN BIN=4 ELSE00000100 WHEN BIN=4 ELSE00000101 WHEN BIN=5 ELSE00000101 WHEN BIN=5 ELSE00000110 WHEN BIN=6 ELSE00000110 WHEN BIN=6 ELSE00000111 WHEN BIN=7 ELSE00000111 WHEN BIN=7 ELSE

49、00001000 WHEN BIN=8 ELSE00001000 WHEN BIN=8 ELSE00001001 WHEN BIN=9 ELSE00001001 WHEN BIN=9 ELSE00010000 WHEN BIN=10 ELSE00010000 WHEN BIN=10 ELSE00010001 WHEN BIN=11 ELSE00010001 WHEN BIN=11 ELSE00010010 WHEN BIN=12 ELSE00010010 WHEN BIN=12 ELSE00010011 WHEN BIN=13 ELSE00010011 WHEN BIN=13 ELSE0001

50、0100 WHEN BIN=14 ELSE00010100 WHEN BIN=14 ELSE00010101 WHEN BIN=15 ELSE00010101 WHEN BIN=15 ELSE00010110 WHEN BIN=16 ELSE00010110 WHEN BIN=16 ELSE00010111 WHEN BIN=17 ELSE00010111 WHEN BIN=17 ELSE00011000 WHEN BIN=18 ELSE00011000 WHEN BIN=18 ELSE00011001 WHEN BIN=19 ELSE00011001 WHEN BIN=19 ELSE0010