轨至轨运放设计课件.ppt

1、RAIL-to-RAIL OP AMPS轨至轨运放的设计轨至轨运放的设计主要内容主要内容 设计原理 采用电平移位法轨至轨运放的设计 采用恒定电压法实现跨导恒定的设计Op Amp ConfigurationsWhy Rail-to-Rail Differential Input Stage?问题 为什么要提高运放的输入信号共模范围？ 为什么要实现跨导的恒定？How to Obtain a Rail-to-Rail Input Common Mode Range?(a) P-type differential input stage(b) N-type differential input sta

2、geHow to Obtain a Rail-to-Rail Input Common Mode Range?How to Obtain a Rail-to-Rail Input Common Mode Range?combining a PMOS and a NMOS Differential pairscombining a PMOS and a NMOS Differential pairsWhy is a Constant Gm needed ?Techniques for N-P ComplementaryRail-to-Rail Input Stage 1. For input s

3、tages with input transistors working in weak-inversion region, using current complementary circuit to keep the sum of IN and IP constant 126; 2. Using square root circuit to keep constant 31316; 3. and 4. Using current switches to change the tail current of input differential pairs 3456; 4. Using he

4、x-pair structure to control the tail currents of backup pairs 7;Techniques for N-P ComplementaryRail-to-Rail Input Stage( contd ) 5. Using maximum/minimum selection circuit to conduct the output current of the differential pair with larger current, as well as larger gm,to the next stage 89; 6. Using

5、 electronic zener diode to keep constant 10; 7. Using DC level shift circuit to change the input DC level 11. We will analyze them one by one in the following sections. There are still other techniques 1214151718, interested readers may check these references.Rail-to-Rail Input Stage, Structure 2 Ba

6、sic idea For an input differential pair, using a 1st order approximation,Rail-to-Rail Input Stage, Structure 3 346 Using current switches to change the tail current of input differential pairs具体电路Rail-to-Rail Input Stage, Structure 6 89 Using Maximum/Minimum selection circuitThe block diagram最大电流选择电

7、路Rail-to-Rail Input Stage, Structure 7 Using DC shifting circuit to change the input DC level具体电路Rail-to-rail amplifier with Zener diodeSummary and Comparison进一步研究的问题 Mismatch between N-channel and P-channel transconductors Transition Region CMRR degradation (40-60 dB) NonlinearityReferences I1 J. F

8、. Duque-Carrillo, J. M. Carillo, J. L. Ausin, and E. Sanchez-Sinencio, “Robust and universal constant-gm circuit technique,” Electronics Letters, vol. 38, no. 9, pp. 396-397, Apr. 2002. 2 M. Wang, T.L. Mayhugh, S.H.K. Embabi, and E. Sanchez-Sinencio, “Constant-gm Rail-to-Rail CMOS Op-Amp Input Stage

9、 with Overlapped Transition Regions,” IEEE J.of Solid State Circuits, vol. 34, no. 2, pp. 148-156, Feb. 1999. 3 G. Ferri and W. Sansen, “A Rail-to-Rail Constant-gm Low-Voltage CMOS Operational Transconductance Amplifier,” IEEE J. of Solid State Circuits, vol. 32, no.10, pp. 1563-1567, Oct. 1997. 4 J

10、. Ramirez-Angulo, R.G. Carvajal, J. Tombs, and A. Torralba, “Low-Voltage CMOS Op-Amp with Rail-toRail Input and Output Signal Swing for Continuous-Time Signal Processing Using Multiple-Input Floating-Gate Transistors,” IEEE Trans. On Circuits and Systems II, vol. 48, no. 1, pp. 111-116, Jan 2001. 5

11、J.M. Carrillo, J.F. Duque-Carrillo, G. Torelli, and J.L. Ausin, “General Purpose rail-to-rail input circuit with constant behavior for VLSI cell libraries,” IEEE International Symposium on Circuits and Systems, vol. 3, pp. 607-610, May 2002References II1 J. H. Huijsing, and D. Linebarger, “Low volta

12、ge operational amplifier with rail-to-rail input and output stages,” IEEE Journal of Solid-State Circuits, vol. SC-20, no.6, pp. 1144-1150, December 19852 W.-C. S. Wu, W. J. Helms, J. A. Kuhn, and B. E. Byrkett, “Digital-compatible high-performance operational amplifier with rail-to-rail input and o

13、utput ranges,”IEEE Journal of Solid-State Circuits, vol. 29 , no. 1, pp. 63-66, January 19943 R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F. Wassenaar, and J. H. Huijsing, “CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage,” IEEE Proc. ISCAS 1992

14、, pp. 2876-28794 R. Hogervost, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, “A compact power-efficient 3-V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1505-1513, December 19945 R. Hogervorst, S. M. S

15、afai, and J. H. Huijsing, “A programmable 3-V CMOS railto-rail opamp with gain boosting for driving heavy loads,” IEEE Proc. ISCAS 1995, pp. 1544-15476 J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, “Low-power low-voltageVLSI operational amplifier cells,” IEEE Trans. Circuits and Systems-I, vol

16、. 42. no.11, pp. 841-852, November 1995References ( contd )7 W. Redman-White, “A high bandwidth constant gm, and slew-rate rail-to-rail CMOS input circuit and its application to analog cell for low voltage VLSI systems,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 701-712, May 19978 C.

17、 Hwang, A. Motamed, and M. Ismail, “LV opamp with programmable rail-to-rail constant-gm,” IEEE Proc. ISCAS 1997, pp. 1988-19599 C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm input-stage architecture for low-voltage op amps,” IEEE Trans. Circuits and Systems-I, vol.42. no. 11, pp. 886-8

18、95, November 199510 R. Hogervost, J. P. Tero, and J. H. Huijsing, “Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode,” IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp. 1035-1040, July 199611 M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Sn

19、chez-Sinencio,“Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition region,” IEEE Journal of Solid-State Circuits, vol. 34, no. 2, pp. 148-156,February 199912 G. Ferri and W. Sansen, “A rail-to-rail constant-gm low-voltage CMOSoperational transconductance amplifier,” IEEE Jour

20、nal of Solid-State Circuits, vol.32, no. 10, pp. 1563-1567, October 1999References ( contd )13 S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage,” IEEE Journal of Solid-State Circuits,vol. 31, no. 2, pp. 146-156, February 199614 J. H.

21、 Botma, R. F. Wassenaar, and R. J. Wiegerink, “Simple rail-to-rail lowvoltage constant transconductance CMOS input stage in weak inversion,”Electronics Letters, vol. 29, no. 12, pp. 1145-1147, June 199315 V. I. Prodanov and M. M. Green, “Simple rail-to-rail constant transconductance input stage oper

22、ating in strong inversion,” IEEE 39th Midwest Symposium on Circuits and Systems, vol 2, pp. 957-960, August 199616 J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “A low voltage CMOS op amp with a rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage,”IEEE Proc. ISCAS 1993

23、, vol. 2, pp. 1314-1317, May 199317 J. F. Duque-Carrillo, J. M. Valverde, and R. Perez-Aloe, “Constant-gm rail-to-railcommon-mode range input stage with minimum CMRR degradation,” IEEE Journal of Solid-State Circuits, vol. 28, no. 6, pp. 661-666, June 199318 A. L. Coban and P. E. Allen, “A low-volta

24、ge CMOS op amp with rail-to-rail constant-gm input stage and high-gain output stage,” IEEE Proc. ISCAS 1995, vol.2, pp. 1548-1551, April-May 1995References ( contd )19 T. W. Fischer, A.I. Karsilayan, and E. Snchez-Sinencio, “A Rail-to-Rail Amplifier Input Stage with +/-0.35% gm Fluctuation,” IEEE Tr

25、ansactions OnCircuits and Systems I. vol. 52, No. 2, pp271-282, February 2005.20 J. Hu, S. Yan, and E. Snchez-Sinencio, “A Constant-GM Rail-to-Rail Op Amp Input Stage Using Dynamic Current Scaling Techniques,”IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005.21 S. Ya

26、n, J. Hu, T. Song, and E. Snchez-Sinencio, “Constant-gm Techniques for Rail-to-Rail CMOS Input Stages: A Comparative Study,” IEEE International Symposium on Circuits and Systems 2005, Kobe, Japan, May 23-26, 2005.22 T. Song, J. Hu, X. Li, S. Yan and E. Snchez-Sinencio, A Robust and ScalableConstant

27、gm Rail-to-Rail CMOS Input Stage with Dynamic Feedback for VLSI Cell Libraries, IEEE Transactions on Circuits and Systems I, pp804-816, Vol. 55, Issue 3, April 2008.一种采用电平移位法的恒跨导轨至轨运放的设计设计指标参数名参数名 设计值设计值 电源电压（VDD） 3.3v 开环增益（RL=10k，CL=10pf）80dB相位裕量（RL=10k，CL=10pf）60度单位增益带宽（RL=10k，CL=10pf）5MHz转换速度 （CL

28、=10pf）10v/us共模抑制比80dB电源抑制比80dB输入共模范围0-3.3v输出摆幅0-3.3v跨导变化率5% 轨至轨特点一、输入输出信号范围尽可能大，从Vss到Vdd。二、输入级的跨导在共模输入电压范围内基本保持恒定。互补差分输入级1、低共模输入：PMOS饱和，NMOS截止2、高共模输入：NMOS饱和，PMOS截止3、输入级最小电源电压：Vsup=Vsgp+Vgsn+2Vdsat 4、共模输入范围为VSSVcmVDD dsatgsnsgpVVVV2supPMOS/NMOS互补差分对的致命缺陷：在整个共模输入范围内，输入电路的总跨导不恒定。 在两对MOS管同时导通时，其总跨导是其它部分

29、的2倍。 电平移位法恒定跨导平移PMOS对或者NMOS对的跨导曲线，使中间重合的部分正好为恒定的常数，且同非重合部分相等。PMOS对左平移法的原理图 一、原理 1、首先要求非重叠部分mnmpgg112 (/) (/)mnnDnnD bngKWL IKWL I3 (/)mppD bpgKWLI即需满足：D bnD bpII13()()npK W LK W L和2、确定平移的量也就是讨论NMOS（或PMOS）对的跨导的2个转折点。 二、平移电路采用输入端接入共源电路的方法。利用MOS管的栅源电压来抬高或降低输入共模电压的范围从而达到平移跨导曲线的目的。这里采用的是PMOS对的左平移法。mpg5SG

30、V利用Mb2，Mb3，M5，M6构成共源电路来对PMOS差分对的跨导进行平移，平移的大小为三、半定量分析1、NMOS管M3开始工作， ，得出 3GSthnVV()3()CMSSDS Mbn satGSsatVVVVCMSSDS MbnthnVVVV2、Vcm增大，直到M3，M4，Mbn都进入饱和区，得出 以上两个式子就是NMOS对的跨导 的转折点。 mng同理，可以求出PMOS对的2个转折点，如下：3、Vcm从Vdd减小到M1开始导通得出 5|DDSD MbpthpSGVcmVVVV4、Vcm再减小时，M1，M2，Mbp进入饱和状态，得出()1()5DDSD Mbp satSGsatSGVcm

31、VVVV根据电平位移法的原理，得出以下方程式： 5()3()|DDSD MbpthpSGSSDS Mbn satGSsatVVVVVVV()1SG5DDSD Mbp satSGsatSSDS MbnthnVVVVVVV（）简化后，两式相减可得出： 1()()3()()|SGsatthpSD Mbp satGSsatthnDS Mbn satVVVVVV1322 () () () ()ppnnpmbppmnmbnnmIIIIWWWWKKKKLLLL分解为22 () ()pnnmbnpmbpIIWWKKLL即npII(/):(/) :mbnmbppnWLWLKK所以满足：这两个条件。 和可知 M1

32、和M3的宽长比之比。5()3()|SGDDSSDS Mbn satGSsatthpVVVVVV由可算出5SGV5552 ()DSGthppIVVWKL5DI52DD MbII由得由可得出Mb2的宽长比。 ClassAB输出级结构1g s ns g pd ds sVVVVVmosmos管工作在饱和区时管工作在饱和区时122|pnddssthnthpPnpnIIVVVVVWWKKLLpnpnWWKKKLL令1(|)2npddssthnthpKIIVVVVV则满足满足输出跨导恒定输出跨导恒定Rail to RailRail to Rail电路的实际宽长比电路的实际宽长比的手工计算的手工计算从从CSM

33、C 0.5um MIX工艺库文件中得到工艺参数工艺库文件中得到工艺参数2n109/oxCA V2p66.1/oxCA V,0.7016th nVV,0.9508th pVV 一、输入级参数计算30bnoIuA设设0.2ds mbnsoVVRail to Rail Rail to Rail 输入级实际电路图输入级实际电路图22022 3013.714()109.1 0.2bnombnngs mbnthnIWLK VV222 3025(|)61.1 0.04bpombppsg mbnthpIWLK VV1140m nm nWSL按照平移法原理的分析按照平移法原理的分析 取取1171.471.5m

34、pm pWSL3140m nSS则则1| 3.3 (0.7 0.2) 0.95 0.2/ 3 1.33mbnshiftDDG mbnthpm nIVVVVv设平移电路的电流设平移电路的电流335d msIuA335() 25 2930MSS再计算再计算122 35861.1 (1.33 0.95)MSS实际的实际的rail-to-rail输出级电路图输出级电路图3210/10100LISRCVspfuA3233100IIuAm a x4 0 0o u tIu A则303033GGSGSVVVG30由前级决定为常数，确定302.45GSVV这里设2.25v。再综合考虑为保证再综合考虑为保证M30

35、-M31能工作在饱和区，设能工作在饱和区，设10.8Vv32210018.161.1 (0.85 2 2)S 得出317S 30222 1527.5109/(0.80.7)ASA V二、输出级参数计算12223323322023242322521032033()m pmmmmmomoosogggggAVggggggggg3233mmgg中间级共源共栅电路图三、中间级共源共栅参数计算总增益0dgI122233222222223223210000()3()m pmmmmmggggAVgIgII根据设计指标和电路原理手工计算得出的MOS宽长比 Rail_To_Rail放大器放大器采用恒定电压法实现跨

36、导恒定的设计采用恒定电压法实现跨导恒定的设计结构与原理9113131313g2()2()2()4882mmnnnnrefnrefrefIWWWgkIkkIIILLL10211 111111g2()2()2()4882mmpppprefprefrefIWWWgkIkkIIILLL当共模信号Vicm很大时，此时只有NMOS差分对(M13,M14)导通，PMOS差分对(M11,M12)截止，此时的跨导大小为： 当共模信号Vicm很小时，此时只有PMOS差分对（M11,M12）导通，NMOS差分对（M13,M14）截止，此时的跨导大小为：结构与原理 当共模信号Vicm处于中间时，此时NMOS、PMOS

37、差分对均会导通，此时的跨导大小为：3131311 11g2()2()8828mmnmpnpnrefprefrefWWggkIkIIIILL注：这里所有的推导是假设()()npnnppWWkkLL每个管子通过的电流为4Iref 中间跨导是两边跨导的一倍随着共模信号的增大互补差分对的工作情况 NMOS差分对导通PMOS差分对导通NMOS/PMOS差分对同时导通VICM 逐渐增大解决方案 保持跨导恒定的方法 降低中间跨导 1）减少共模信号处于中间状态时电流 2）怎样控制电流使得在 处于较大以及较小的情况下分别保持NMOS、PMOS差分对中的电流保持不变4Iref 增加并联二极管支路定量的计算313

38、1311 111111g2()2()2 28mmnmpnpWWggkIkIIILL123g=ggmmm11131214refIIIII 解之得icmV处于中间状态时,流过NMOS、PMOS差分对中的电流为Iref而不是4Iref 二极管支路的电流为多少？ 二极管支路一是，稳压管的制作工艺与标准的CMOS工艺是不兼容的。二是，在稳压管正常工作的情况之下，如何精确的控制流过其中的电流为6refI显然这是很难做到的。 refZTNTP2 4IVVV2 当 处于较大时，由于NMOS差分对导通，则 ，PMOS差分对不导通，则 从而稳压电路是不导通的。当 处于较小时，与上面的分析同理。 ref13TNON

39、TN2 4IVVGSVV采用稳压管处于中间状态的情况 此时PMOS，NMOS差分对均处于导通状态，如果没有稳压管的情况下， 显然 这时稳压管正常的导通。refrefAB1113TPTN2 4I2 4IV= V+VSGGSVVrefZTNTP2IVVV2 ABZVV处于中间状态时，流过二极管支路的电流是6IrefD16ONPI2PVD15ONNIV2N其中PNTPTNVV由上面的假设,则 同理可知， 1113SGGSVVM11的栅极G11与M16的栅极G16是等位点16161111()()DDWILWIL15151313()()DDWILWIL管子的尺寸电阻与电容存在的误差 共模电压处于较大以及较小的情况支路有小电流 MOS管导通与截止存在缓慢变化过程 伏安特性非理想 P管与N管非对称 如何消除？