高速串行接口技术详解课件.ppt

1、1Deog-Kyoon JeongSeoul National UniversityHigh-Speed Serial LinkIntegrated System Design Lab. 2 Introduction High-speed I/O overview Hot design issues Design examples SummaryOutlineIntegrated System Design Lab. 3Introduction Moores law Performance & density improvement in digital system1001011021031

2、041051061071081980198419881992199620002004Gates density1001011021031041980198419881992199620002004CPU performanceIntegrated System Design Lab. 4Introduction Moores law1001011021031041980198419881992199620002004CPU performanceMemory access1001011021031041051061071081980198419881992199620002004Gates d

3、ensitySignal pinsGrowing gap limits system performance!Integrated System Design Lab. 5Digital System PerformanceCommunication - boundComputation - bound Performance bottleneck The cost of arithmetic operation is cheap now“Pentium Pro”10 20 cycles / Arithmetic operation70 cycles / DRAM access“Pentium

4、 4”20 30 cycles / Arithmetic operation500 600 cycles / DRAM accessIntegrated System Design Lab. 6Computing System High-speed I/O is needed everywhereNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocal I/OLong distanceSANIntegrated System Design Lab. 7Parallel Bus & Serial LinkGroup data

5、(Bus)Source synchronousMatched traceParallel BusCoreI/OClockDataCoreI/OSerial LinkCoreI/OSerialDataCoreI/OSingle tracePlesiochronousClock embedded in dataClock & data recoveryIntegrated System Design Lab. 8Parallel vs. SerialParallel BusSerial LinkHardware ComplexityLowHighLatencyShortLongSpeed 200M

6、bps / pin 10Gbps / pinor moreManufacturingCostHighLowWorld is moving toward “serial link” or “serial-link-like parallel bus” !Integrated System Design Lab. 9Serial Link ArchitectureReceiverTransmitterPLLFramerPCSSerializerDeframerClock recoveryChannelPCSDeserializerTransmitter + Receiver= Transceive

7、rIntegrated System Design Lab. 10Link ComponentPhaseDetectorLoop-FilterVoltage-ControlledOscillator MCKi( fin )VctrerrorCKo( fout ) Phase-locked Loop (PLL) Frequency multiplication: fout = Mfin Jitter filter Zero-delay bufferIntegrated System Design Lab. 11Link Component High-speed, low voltage swin

8、g interface Usually, differential Small swing - several hundreds mVZ0Z0ChannelDC blockTermination( R = Z0 )VTTVRRToCDRDriverLimiting ampIntegrated System Design Lab. 12Link Component Clock & data recovery (CDR) circuitsNRZ PhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecision

9、circuitDiDoCKr01101001000Integrated System Design Lab. 13Link Performance Metric Eye diagram & jitterRandom bit sequenceTbitEye diagramTbitTiming uncertainty : JitterJitter histogramIdealRealisticIntegrated System Design Lab. 14Link Performance Metric Eye diagram example Near end & far endPLLFramerD

10、eframerClock recoveryChannelIntegrated System Design Lab. 15Link Performance Metric Bit-error rate (BER) In most serial link standards, BER 10-12 is specifiedEye diagramJitter histogramRecovered clockBit error!Jitter PDF = f(x) UIUIdxxfdxxfBER5.05.0)()( UIUIdxxfdxxfBER5.05.0)()(Integrated System Des

11、ign Lab. 16High-Speed Link StandardsNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocal I/OSANDVILVDSEthernetSATASONET/SDHFibreChannelInfiniBandPCI ExpressHyperTransportRDRAMXDRIntegrated System Design Lab. 17Industry Roadmaps0.1G1G10G100GData-rateEthernetSONET/SDHFast EthernetGigabit Et

12、hernet10G EthernetOC-48OC-192OC-768SATAOC-12XAUIGen1 Gen2 Gen3PCI ExpressPCIe1.0 PCIe2.0(?)Fibre ChannelFC-PI-1 FC-PI-210GFCDVIVGAUXGASXGAYear 2005, world is here!Integrated System Design Lab. 18Digital Visual Interface (DVI) PC display CRT (analog) LCD (digital) DVI Digital Visual InterfaceAnalogDi

13、gitalIntegrated System Design Lab. 19Digital Visual Interface (DVI) TMDS Transition minimized differential signaling EMI reductionTMDSencoderPLLGraphiccontrollerTMDSdecoderPLLDisplaycontrollerIntegrated System Design Lab. 20High Definition Multimedia Interface (HDMI) HDMI High-definition multi-media

14、 interface Digital video + multi-channel audio interface for consumer electronics Compatible with DVIIntegrated System Design Lab. 21Serial ATA (SATA) Next generation ATA bus within PC box Eliminates fat ATA cables Point-to-point connection 1.5G/3G/6GParallel ATA cablingSerial ATA cablingIntegrated

15、System Design Lab. 22Transceiver Chip Design Technology CMOS, InP, GaAs, SiGe, BiCMOS CMOS will be the eventual winner Low cost, high-integrity Speed Power consumption Area Level of integration Mixed-signal SoC Serial link interface + digital circuitryTrade-off!Integrated System Design Lab. 23Hot De

16、sign IssuesPLLFramerDeframerClock recovery CMOS serial link transceiverIntegrated System Design Lab. 24Hot Design IssuesPLLFramerDeframerClock recovery CMOS serial link transceiverPrecise-timing generation- High-frequency, low jitter PLLHigh-performance CDR- High-speed NRZ PD- Various CDR architectu

17、resHigh-speed CMOS circuits- Logic gates, analog bufferChannel loss compensation- EqualizerIntegrated System Design Lab. 25Precise Timing generation VCO noise PLL jitter Data eye jitter Low noise, high-frequency VCO is requiredPhaseDetectorLoop-FilterVoltage-ControlledOscillator MCKi( fin )Vctrerror

18、CKo( fout )Integrated System Design Lab. 26Voltage-Controlled OscillatorPoorNoiseGoodLowFrequencyHighWideTuning rangeNarrowLowCostHighRing oscillatorM stagesdMTf21 Td = C V / ILC tank oscillatorParasitic resistanceNegative gmOn-chip spiral LOn-chip varactorvarLCfp p21 Integrated System Design Lab. 2

19、7High-Speed CMOS CircuitsCurrent-mode logic (CML)ZLNMOSLogic R R + L R + T-coilCMOS logicNMOSPull-downPMOSPull-upComplementaryIntermediateSpeedFastSmallAreaLargeSmallPower consumptionLarge High-speed logic gatesIntegrated System Design Lab. 28High-Speed CMOS Circuits High-speed buffer with on-chip i

20、nductor Shunt peaking Inserts a zero at high frequency Series peaking Isolates the buffer output node from load capacitanceNormalShunt peakingShunt peakingShunt seriespeakingSeries peakingShunt double-series peakingSeries peakingIntegrated System Design Lab. 29High-Speed CDR NRZ PD Hogge phase-detec

21、tor Linear PD Full-rate operation Matched up/down when locked Less noisyD QD QDNUPCKDABDCKABUPDNArea difference Phase errorVery short pulse!Phase error Clock earlyIntegrated System Design Lab. 30High-Speed CDR NRZ PD Alexander phase-detector Binary PD With multi-phase clock Time interleaving Bang-ba

22、ng control Noisy D0D1ABTClock earlyD0D1ABTClock lateUPDND QD QD QD QBADNUPTCKDIntegrated System Design Lab. 31High-Speed CDR Architectures PLL-based CDR 1 PLL / channel Precise phase control Suitable for high-speed, high-performance systemNRZ PhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVct

23、rerrorDoCKrDecision circuitEither linear or binaryIntegrated System Design Lab. 32Channel Loss Band-limited channel Bonding wire, PCB trace, connector, cable Skin effect Dielectric loss0246810-60-50-40-30-20-100frequency GHzAttenuation dB9 FR4, via stub26 FR4,via stub26 FR49 FR4Integrated System Des

24、ign Lab. 33Channel Loss Effect Inter-symbol interference (ISI)00010111Time-4TB-3TB-2TB-TBTB2TB3TB4TB0AmplitudeIntegrated System Design Lab. 34Channel Loss Compensation TX Pre-emphasisWithpre-emphasisWithoutpre-emphasisIntegrated System Design Lab. 35Channel Loss Compensation RX Equalization Continuo

25、us time equalizergDinDoutHigh-pass filterCapacitivedegenerationIntegrated System Design Lab. 36Design Examples 40Gbps transmitter Process 0.13 CMOS Power 2.8W Area 2.5 3.6 mm2 Features 20G standing-wave VCO Shunt-double series peaking at 10/20/40G buffers Active feedback at 20G divider 410 on-chip s

26、piral inductorsIntegrated System Design Lab. 37Design Examples 40G transmitter Standing wave VCOVaractorsIntegrated System Design Lab. 38Design Examples 40G transmitter test resultsTest chip25psIntegrated System Design Lab. 39Design Examples Features 10G LC-tank VCO PLL-based 10G CDR DLL-based quad

27、3.125G CDR (XAUI) Integrated with digital control core 10G Ethernet PHY with XAUI interface Process 0.13 CMOS Power 900mW Area 5 5 mm2Integrated System Design Lab. 40Design Examples 3.5G continuous time adaptive equalizer Process 0.18 CMOS Area 0.48 0.73 mm2 Power 80mW 3.5GCable inputCable outputEqu

28、alizer output Features 3.5G Adaptive mode 5G Manual modeIntegrated System Design Lab. 41Summary Now, digital system performance is bounded by system I/O bandwidth In industry, serial link I/O is going mainstream Toward low-cost, high-bandwidth system I/O, we should overcome several physical limitations such as Jitter & noise Channel loss Device speed