《电子技术数字基础-Digital-Fundam课件.ppt

1、.1Chapter 8 Counters (and the Sequential Logic).2Contentsw Introductionw Analysis of the Sequential Logicw Countersw Design of Sequential Logics.38-0 Introductionw The digital electronic logic is classified as the combinational logic and the sequential logic. w (数字电路分为：数字电路分为：组合逻辑电路及时序逻辑电路组合逻辑电路及时序逻

2、辑电路)w The sequential logic includes the combinational logic section and the memory section.48-0 Introduction The logic diagram for the general sequential logic输出方程驱动方程状态方程.58-0 Introductionw The sequential logic is classified as the asynchronous one and synchronous one (异步时序异步时序电路和同步时序电路）电路和同步时序电路）.

3、w The analysis and design of the sequential logic is discussed in this chapter. And the counter is the most useful device.68-2 Synchronous Counter Operation (同步计数器）& Analysis of the Sequential Logic（时序电路分析）w Synchronous (同步同步): Events that have a fixed time relationship with each other.w Synchronous

4、 counter: the counter whose flip-flop (FF) are clocked at the same time by a common clock pulse.78-2-1 Analysis of the Sequential Logicw Whats the function of the following logic diagram?How to analyze this diagram? .88-2-1 Analysis of the Sequential Logic -ProcedureProcedure: Write down the clock a

5、nd excitation expressions for each FF.2. Get their state expressions by replacing the logic expression for the FF with its excitation expression.写出每个触发器的时钟方程和驱动方程；写出每个触发器的时钟方程和驱动方程；2. 2. 将驱动方程代入触发器的特性方程，得到状态方程组；将驱动方程代入触发器的特性方程，得到状态方程组；.98-2-1 Analysis of the Sequential Logic -Procedure3. 3. 写出输出方程；写

6、出输出方程；5. 5. 说明电路的逻辑功能。说明电路的逻辑功能。4. 4. 依次假定依次假定初态初态, ,计算计算次态次态, ,画出画出状态转换图状态转换图( (表表) )或或 时序波形图时序波形图 。3. Write down the output expression;4. Assume the present state, and analyze the next state, and draw its state diagram (状态转换图状态转换图) /state sequence table(状态转换表状态转换表)or its timing diagram （时序图）（时序图）.

7、5. Determine the logic function of the logic diagram.108-2-1 Analysis of the Sequential Logic Example1w Ex.1 Determine the logic function.01100101)(. 1QKJKJCLKCPCPSynchronous Sequential LogicWrite down the clock and excitation expressions for each FF.Toggle at the positive edge.nnnQKQJQ1. 2)()(. 210

8、1011010CLKQQQQQCLKQQnnnnnnnT FFJ=K=1.118-2-1 Analysis of the Sequential Logic Example14. Assume the present sate, and analyze the next state, and draw its state diagram / state sequence table or its timing diagram.)()(. 2101011010CLKQQQQQCLKQQnnnnnnn.128-2-1 1 Analysis of the Sequential Logic State

9、Sequence Table (状态转换表)1001QQ1101QQ0001QQ0101QQ)()(. 2101011010CLKQQQQQCLKQQnnState Sequence Table.138-2-1 Analysis of the Sequential Logic State Diagram (状态转换图)State Sequence TableState Diagram.148-2-1 Analysis of the Sequential Logic Timing Diagram (时序图)Timing Diagram.158-2-2 A 2-Bit Synchronous Bi

10、nary CounterA 2-bit synchronous binary counter(2位同步二进制位同步二进制/4进制进制 加法计数器）加法计数器）.168-2-3 A 3-Bit Synchronous Binary Counterw Ex.2 Determine the logic function.178-2-3 A 3-Bit Synchronous Binary Counter.188-2-3 A 3-Bit Synchronous Binary CounterA 3-bit synchronous binary counter(3位同步二进制位同步二进制/8进制进制 加法

11、计数器）加法计数器）.198-2-4 A 4-Bit Synchronous Decade Counter.208-2-4 A 4-Bit Synchronous Decade Counter.218-2-4 A 4-Bit Synchronous Decade CounterA 1-bit synchronous decade counter(同步十进制加法计数器）同步十进制加法计数器）.228-1 Asynchronous Counter Operation (异步计数器异步计数器)w Asynchronous: refers to events that do not have a fi

12、xed time relationship with each other and, generally, do not occur at the same time.w Asynchronous counter: counter in which the FF do not change states at exactly the same time because they do not have a common clock pulse.238-1-1 Analysis of Asynchronous Sequential Logicw Determine the logic funct

13、ion.Asynchronous Sequential Logic.248-1-1 Analysis of Asynchronous Sequential Logic)()()()(exp. 103120100QCPQCPQCPcpCPressionsClock.258-1-1 Analysis of Asynchronous Sequential Logic1,11,1)2(32132213100KQQJKJKQJKJnnnQKQJQ1. 2)()()()(. 20321131212013110010QQQQQQQQQQQQcpQQnnnn.268-1-1 Analysis of Async

14、hronous Sequential Logic30. 3QQC .278-1-1 Analysis of Asynchronous Sequential Logic)()()()(. 20321131212013110010QQQQQQQQQQQQcpQQnnnn30. 3QQC .288-1-1 Analysis of Asynchronous Sequential LogicState Sequence TableState DiagramA asynchronous decade counter(异步十进制加法计数器）异步十进制加法计数器）.298-1-2 Some Useful Co

15、nceptsw Valid states (used states) (有效状态) states used by the diagram in normal operation.w Invalid states (unused states)(无效状态） states which arent used by the diagram in normal operation.308-1-2 Some Useful ConceptsValid StatesInvalid StatesValid CycleInvalid Cycle.318-1-2 Some Useful Conceptsw Vali

16、d Cycle (有效循环) Cycle that includes the valid states.w Invalid Cycle(无效循环） Cycle that includes the invalid states.328-1-2 Some Useful Conceptsw Startup automatically (自启动功能) If a logic diagram doesnt have invalid cycle(无效循环), it can startup automatically. ( (电路进入无效状态之后电路进入无效状态之后, ,在在CPCP脉冲作用下脉冲作用下, ,

17、能自动返回有能自动返回有效循环效循环, ,称电路能够自启动称电路能够自启动, ,否则为不能自启动）否则为不能自启动）w Self-startup check (自启动检查) Check if all the invalid states can enter the valid cycle automatically. .33State DiagramStartup automaticallySelf-startup check.348-3 Counters 8-3-1 Categories of CountersOthers）(counter Up/Down ）( counter Down ）

18、( counter Up可逆计数器减法计数器加法计数器The counter can be classified as the following categories:）( counter sSynchronou）( counter usAsynchrono同步计数器异步数器.358-3-1 Categories of Counters）( counter Others）( counter Decade）( counter Binary 其他计数器十进制计数器二进制计数器Modulus-2 counter (2进制）进制）Modulus-10 counter (10进制）进制）Modulus

19、-60 counter (60进制）进制）Modulus-M counter (M进制进制,任意进制）任意进制）.368-2-5 Synchronous Binary CountersQn+1=TQn+TQnC=Q0Q1Q2Q3Negative edge- triggered .378-2-5 Synchronous Binary Countersf01/2f01/4f01/8f01/16f01/16f0The counter is also called the frequency divider (分频器分频器).C=Q0Q1Q2Q3.388-2-5 Synchronous Binary

20、Counters -74161 MSI modulus-16 counterCounter, Divider,Modulus-16(16进制进制).398-2-5 74161 MSI modulus-16 counterParallel data inputs( (并行输入端）并行输入端） Data outputs/States Clock PulseActive at the positive edgeENT,ENP: Enable Pins .408-2-5 74161 MSI modulus-16 counter.418-2-5 74161 MSI modulus-16 counterP

21、reset input (Load)(预置端）预置端）(同步预置同步预置)Active-low, synchronously Clear input (清零端）清零端）(异步清零异步清零)Active-low, asynchronously .428-2-5 74161 MSI modulus-16 counterAt the terminal count of 15, RCO=1.Ripple clock output(进位脉冲进位脉冲).438-2-5 74161 MSI modulus-16 counterState DiagramTiming Diagram.448-2-5 74161

22、/74163 MSI modulus-16 counterCLRLOADENPENTLogic Function Table(功能表）功能表） for 74161/74163.458-2-5 74161/74163 MSI modulus-16 counterClear input (清零端）清零端）(异步清零异步清零)Active-low, asynchronously .468-2-5 74161/74163 MSI modulus-16 counterPreset input (Load)(预置端）预置端）(同步预置同步预置)Active-low, synchronously .478-

23、2-5 74161/74163 MSI modulus-16 counterOnly when both of EP and ET are active, is the counter enabled (in counter operation).The outputs plus one at the positive-edge of CP .488-2-5 74161/74163 MSI modulus-16 counterOnly when both of EP and ET are active, is the counter enabled (in counter operation)

24、.498-2-5 74160 MSI modulus-10 counter74160 synchronous BCD decade counter (CTR DIV 10 modulus-10, 10 states).508-2-5 74160 MSI modulus-10 counterClear asynchronously 异步清零异步清零The clear input is active-LOW.518-2-5 74160 MSI modulus-10 counterA timing diagram showing the counter being preset to count 7

25、 (0111).Preset synchronously 同步预置同步预置When the preset input is nonactive, the parallel inputs have no use.The outputs are preset to the corresponding data input only at the active edge of CP.528-2-5 74160 MSI modulus-10 counterWhen the terminal count is 9 (TC=9), RCO=1.538-2-5 74160 MSI modulus-10 co

26、unterIf any of ENP and ENT is nonactive (LOW), the outputs are disabled, remain in present states.548-3 Up/Down Synchronous Counters(可逆可逆/加减计数器加减计数器)w By the control of the up/down input, the counter, on one hand, can increase one by one; on the other hand, can also decrease one by one.w This kind o

27、f counter is called up/down (加减加减) one, bidirectional （可逆）（可逆）counter, also.558-3 Up/Down Synchronous CountersA basic 3-bit up/down synchronous counter.568-3 Up/Down Synchronous CountersUp/down sequence for a 3-bit binary counterState Sequence Table for a 3-bit binary counter.578-3 Up/Down Synchrono

28、us CountersState DiagramUp sequenceDown sequence.588-3 Up/Down Synchronous Countersw Logic function table for MSI 74191- a synchronous modulus-16 up/down counterPreset Asynchronously 异步预置异步预置LOADCTEN.598-3 Up/Down Synchronous Countersw Logic symbol for MSI 74190- a synchronous modulus-10 up/down cou

29、nter.608-3 Up/Down Synchronous CountersTiming Example For a 74190Preset Asynchronously 异步预置异步预置.618-4 Design of Sequential Logics(时序电路设计)Sequential logic designSSI Sequential logic design(小规模小规模)- Design sequential logic using flip-flops 用触发器设计时序电路用触发器设计时序电路MSI Sequential logic design(中规模中规模)- Desig

30、n modulus-M counter using MSI modulus-N counter用用N进制中规模集成计数器设计任意进制中规模集成计数器设计任意M进制计进制计数器数器.628-4-1 SSI Sequential logic design- Sequential Logics Design using FFProcedure:w Step 1: Convert the given problem to a logic problem. Assume the input, output and state variables.w Step 2: Get its state diagr

31、am.w Step 3: Get its state sequence table.w Step 4: According to the number of the states, draw a corresponding number-variable K-map. .638-4-1 Sequential Logics Design using FFw Step 5: Get the state expressions using K-map.w Step 6: Choose the needed flip-flop. w Step 7: Get the excitation express

32、ions according to the state expressions and logic expression for the corresponding flip-flop.w Step 8: Sketch the logic diagram.648-4-1 Sequential Logics Design using FFExample 1Ex.1: Design a modulus-13 counter with cascaded output.Step 1: Assume the input, output and state variables. Output: CStat

33、e variables: S0,S1S12State diagram.658-4-1 Sequential Logics Design using FFExample 113 states: 4 flip-fops (13 =24)Step 2: State sequence table.668-4-1 Sequential Logics Design using FFExample 1w Step 3: next-state K-map.Present state:0000Next state: 0001 Output: 0Dont care conditions.678-4-1 Seque

34、ntial Logics Design using FFExample 1w Step 4: Get k-map for each state. (Optional).688-4-1 Sequential Logics Design using FFExample 1Step 5: Get the state expressions.698-4-1 Sequential Logics Design using FFExample 1Step 5: Get the output expression.C=Q3Q2Step 6: Choose the flip-flop: J-K flip-flo

35、p.708-4-1 Sequential Logics Design using FFExample 1Step 7: Get the excitation expression.nnnQKQJQ113323210QQQQQQQn.718-4-1 Sequential Logics Design using FFExample 1Step 8: Draw the logic diagram.C=Q3Q2.728-4-1 Sequential Logics Design using FFExample 1w Step 9: Self-startup check (自启动检查自启动检查)It ca

36、n startup automatically.13323210QQ QQ Q Q Qn.738-4-1 Sequential Logics Design using FFExample 2Ex. 2: Design a logic diagram that can check the series data. When there are three or more than three HIGH inputs in series, the output is 1; otherwise , the output is 0. 设计一个串行数据检测器。当连续输入设计一个串行数据检测器。当连续输入

37、3个或个或3个以上个以上1的时候，输出为的时候，输出为1；否则为；否则为0。 .748-4-1 Sequential Logics Design using FFExample 2w Step 1: Analyze the problem, assume the input/output variables, and get its state diagram/state sequence table.Assume:X: the input variable;Y: the output variable;States: S0 the input is 0; S1 there is only o

38、ne HIGH input. S2 there is two HIGH inputs in series. S3 there is three or more than three HIGH inputs in series.758-4-1 Sequential Logics Design using FFExample 2w Step 2: State sequence tableEquivalent States(等价状态等价状态)The input.768-4-1 Sequential Logics Design using FFExample 2Step 3: K-map0001103

39、 states: 2 flip-fops (3 N, more than one MSI device is needed.1088-4-3 Sequential Logics Design using MSI Counterw1. MNSkip N-M statesTwo methods:(1) Implement it using the CLEAR (RESET) input (generally the CLEAR input is asynchronous). (利用清零端，反馈归零法)(2) Implement it using the PRESET input. (Some of

40、 the PRESET input are asynchronous, and others are synchronous) (利用预置端，置数法).1098-4-3 Sequential Logics Design using MSI CounterMomentary/Astable state (瞬态), not included in the valid cycle.异步清零，瞬态不包括在有效循环中异步清零，瞬态不包括在有效循环中Preset the states at any state可在任意状态下进行预置可在任意状态下进行预置同步预置没有瞬态，异频预置有瞬态。同步预置没有瞬态，异

41、频预置有瞬态。.1108-4-3 Sequential Logics Design using MSI CounterOnly when both of EP and ET are active, is the counter enabled (in counter operation).w Ex. 1 Implement a modulus-6 counter using 74160.w Logic Function Table for 74160Clear inputActive-low, asynchronously(异步清零) Preset input (Load)Active-low

42、, synchronously(同步预置) .1118-4-3 Sequential Logics Design using MSI CounterModulus-10 Counter.1128-4-3 Sequential Logics Design using MSI Counter(1) Logic circuit using the Clear/Reset input.0001011001010100001000110000/0/0/0/0/1/1Problem: ?Its too short to clear each flip-flop.Momentary state.1138-4

43、-3 Sequential Logics Design using MSI CounterThe improved circuit:Remain active (LOW) until CP becomes LOW.1148-4-2 Sequential Logics Design using MSI Counter(2) Logic circuit using the Preset input.000101010100001000110000/0/0/0/0/1/1Stable stateNotice the levels of the parallel inputs.1158-4-3 Seq

44、uential Logics Design using MSI Counter000110010100001000110000/0/0/0/0/1/0Stable stateNotice the levels of the parallel inputs.1168-4-3 Sequential Logics Design using MSI CounterComparison: Different preset states.Different cascaded output.1. Different states in which to preset.1178-4-3 Sequential

45、Logics Design using MSI CounterEx. Design a modulus-24 counter using 74LS160.Method 1: 24=64.1188-4-3 Sequential Logics Design using MSI Counterw Method 2: 1010=100 24.119Assignment 1/3wAnalyze the logic function of the following logic diagram.wPage510- 8,10,13.120Assignment 2/33. Assume the sate diagram for one sequential circuit shown as the following diagram. Sketch the logic diagram to implement the given state diagram with JK flip-flops.101000111011010.121Assignment 3/34. Determine the overall modulus of the following logic diagram.