DRAM内存颗粒测试简介PPT课件.pptx

1、Introduction to DRAM Testing- DRAM inside team- 2015.MayAgendanBasis of TestingnTypical DRAM Testing FlownBurn-innDC Test (Open/Short, Leakage, IDD)nFunctional Test & Test PatternnSpeed TestDRAM ManufactureWaferAssemblyFinal TestingFinal ProductWhy Testing?To screen out defectWafer defectAssembly de

2、fectMake sure product meet spec of customerVoltage guard bandTemperature guard bandTiming guard bandComplex test patternCollect data for design & process improvementQualityReliabilityCostEfficiencyIC Test MethodologyIC TesterPPSDriverComparatorDUT* DUT = Device Under TestPower SupplyOutputInputTesti

3、ng of a DUT: 1. To connect PPS, Driver, Comparator & GND. 2. To apply power to DUT. 3. To input data to DUT (Address, Control Command, Data) 4. To compare output with “expect value” and judge PASS/FAILBasic Test SignalDigital Waveform ElementsLogicVoltageTimingTypical DRAM Final Test FlowBurn-in MBT

4、 (Monitor Burn in Test): Stress to screen out Early Failures TBT (Test Burn in Test): Long time pattern test Very Low Speed(5-20MHz), High Parallel Test (10-20Kpcs/oven), Low CostCore Test DC Test Functional Test Low Speed (DDR3 667MHz), Typical tester Advantest T5588 + 512DUT HiFixSpeed Test Speed

5、& AC Timing Test Full Speed (DDR3 1600MHz and above), Advantest T5503 + 256DUT HiFixBackend Marking Ball Scan Visual Inspection Baking Vacuum Pack DRAM Burn-in (MBT)High Temperature Stress (125degC)High Voltage StressStressful Pattern BIOperation TimeFailure RateInfant MortalityNormal LifeWorn outNe

6、w productMature productBath CurveDRAM Burn-in (TBT)Multiple temperature tested (e.g. 88C, 25C, -10C)Long test time at low speedPatterns cover all cell arraysNo Stressful conditionHigh parallel test count, low costBoth MBT and TBT does NOT test DC (Ando Oven)DRAM Advantest TestOpen/Short testLeakage

7、testIDD testDifferent parameter & Pattern for each functionTo check DRAM can operate functionallyTiming test different speed gradeDC Test VCCVCCDC Test Open ShortPurpose: Check connection between pins and test fixture Check if pin to pin is short in IC package Check if pin to wafer pad has open in I

8、C package Check if protection diodes work on die It is a quick electrical check to determine if it is safe to apply power Also called Continuity TestDC Test Open ShortFailure Mode:a) Wafer ProblemDefect of diodeb) Assembly ProblemWire bondingSolder ballc) Contact ProblemSocket issueCore CircuitDefec

9、tive diodeSocket Pogo Pin defectWire touchedDC Test Open ShortO/S Test Condition:ProcedureGround all pins ( including VDD)Using PMU force 100 uA, one pin at a timeMeasure voltageFail open test if the voltage is greater than 1.5 VFail short test if the voltage is less than 0.2 V100uA0.65 VPMUforcesen

10、seforceMeasureVss=0Vdd=0100uAFail OpenPassFail Short 1.5V 0.2 V1.5 V-100uA-0.65 VPMUforcesenseforceMeasureVss=0Vdd=0-100uAISVMOther=0Typical -0.65VDC Test LeakagePurpose: Verify resistance of pin to VDD/VSS is high enough Verify resistance of pin to pins is high enough Identify process problem in CM

11、OS device DC Test LeakageILIH/ILIL: Input Leakage High/Low To verify input buffers offer a high resistance No preconditioning pattern appliedILOH/ILOL: Output Leakage High/Low To verify tri-state output buffers offer a high resistance in off state Test requires preconditioning pattern Performed only

12、 on three-state outputs and bi-directional pinsDC Test LeakageFailure Mode:a) Wafer problemb) Assembly problemc) Socket Contact problem (short)Die crackBall touch (Short)DC Test Input Leakage LowProcedureApply VDDmax (2.0V)Pre-condition all input pins to logic 1 (high voltage)Using PMU (Parametric M

13、easure Unit) force Ground to tested pinWait for 1 to 5 msecMeasure current of tested pinFail IIL test if the current is less than 1.5 uAPassFail 1.5 uA2.0 V10nAPMUforceMeasureVss=0VDDmaxILIHVLSICore“1”“0” all input pins = 0VONOFFDC Test Output Leakage LowProcedureApply VDDmax (2.0V)Pre-condition the

14、 DUT to tristate with specific patternWait a specific timeUsing PMU force VDDMAX to tested I/O pinMeasure currentFail IOH test if the current is greater than +4.5uA or less than -4.5uAPassFailGT 4.5 uA0.0 V-10nAPMUforceMeasureVss=0VDDmaxILOLVLSICoreOFFOFFPre-condition Pattern 1/0FailLT -4.5 uA“0”All

15、 input pins = 2.3VAll output pins=0V/2.3VDC Test Output Leakage HighProcedureApply VDDmax (2.0V)Pre-condition the DUT to tristate with specific patternWait a specific timeUsing PMU force VDDMAX to tested I/O pinMeasure currentFail IOH test if the current is greater than +4.5uA or less than -4.5uAPas

16、sFailGT 4.5 uA2.0 V10nAPMUforceMeasureVss=0VDDmaxILOHVLSICoreAll input pins = 2.3VAll output pins=0V/2.3VOFFOFFPre-condition Pattern 1/0FailLT -4.5 uA“1”DC Test Test Program ConditionDC Test IDDPurpose:nIDD (or ICC) measures current of Vdd pin in different statesnIt makes sure power consumption not

17、higher than expected.Failure Mode:a)Wafer process issueb)Assembly issuec)Contact issue (VDD, VSS)DC Test Static IDDProcedureUsing PMU to apply VDDmax on VDD pinExecute Pre-condition patternStop the patternWait a specific time Measure current flowing into VDD pins while device is in idleFail IDD test

18、 if the current is greater than IDD spec. ( Normal in mA)PassFailGT spec2.0 V10mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition PatternDC Test Dynamic IDDProcedureUsing PMU to apply VDDmax on VDD pinExecute Pre-condition patternWait a specific time Measure current flowing into VDD pins while

19、device is executing patternFail IDD test if the current is greater than IDD spec. ( Normal in mA)Stop patternPassFailGT spec2.0 V80mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition PatternPre-condition PatternFunction TestTo verify DRAM can operate functionally, we need to do Functional test.-

20、 Easy Function Test (EFT)It check basic IC functionality by reading “0” (or “1”) from all cell after writing “0” (or “1”) in. Typical Test Pattern: March Pattern (e.g. March C-)March C- Algorithm: (w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0); (r0)Operation Count: 10*nScan type: X-Scan (X inc - Y inc), Y-Sca

21、n(Y inc - X inc)Fault Coverage: Most of Failure ModeDRAM Test Pattern (X-scan)YX000110110001101128.DRAM Test March Pattern29.DRAM Test Failure ModeStuck-at Fault (SAF)Coupling Fault (CF)nShorts between data linesnCrosstalk between data linesTransistion Fault (TF)nCell can be set to 0 and not to 1 (o

22、r vice versa) when its operatedAddressing Fault (AF)nAddress line stucknOpen in address linenShorts between address linesnWrong accessnCell stucknDriver stucknData line stuckNeighbor Pattern Sensitive Fault (NPSF)nPattern sensitive interaction between cellsData Retention Fault (DRF)nData can not kep

23、t same status in cell as time passDRAM Test March PatternMarch C- is the most effective31.DRAM Test 1HTDefect ModeOPENLEAKIDDEFTTESTER RELATEDWAFER ISSUEDIE CRACKDIE CHIPSURFACE DAMAGENG DieNON DIENON WIREAE OPENWIRE SHORT WITH WIREWIRE SHORT WITH DIE EDGEWIRE SWEEPNON BROKEN INNER LEADOTHERS: SUSPE

24、CTION FOR FAILAbove table comes from our experiences. It is not covered all of failure modes vs phenomena. So, it is only for your reference.32.DRAM Test Functional TestOther Functional TestCheck Core Function (80% of total test time)Data Retention, ODT, Burst Read/Write, etcDetect Pattern Sensitive

25、 Fault (PSF)0 0 00 1 00 0 00 0 00 0 00 0 033.DRAM Test AC TestAC Parameter TestTo verify IC can work as each timing parameter defined in datasheet Rise and fall time Setup and hold time Delay test Others34.DRAM Test Speed TestTest DRAM at different speed: 1. DDR3-1600(11-11-11) Test 2. DDR3-1333(9-9-9) Test 3. DDR3-1066(7-7-7) Test Test for each timing (tRCD, tRRD) DDR3-1600DDR3-1333Speed Fail35.DRAM Test Test Plan in Program1333Fail1600186636.37.