DDRSDRAM基础知识教育课件.ppt

1、DDRSDRAMDDRSDRAM基础知识基础知识PPTPPT讲座讲座DRAM Basic KnowledgeDRAM Device ArchitectureDRAM Access FlowDRAM Basic CommandsDRAM Command SchedulePage ClosePage OpenBank InterleaveCommands Re-OrderDRAM Controller BasicDRAM Controller Function & ArchitectureAddress Mapping in DRAM ControllerDRAM Basic KnowledgeD

2、RAM Device ArchitectureDRAM Access FlowDRAM Basic CommandsDRAM Command SchedulePage ClosePage OpenBank InterleaveCommands Re-OrderDRAM Controller BasicDRAM Controller Function & ArchitectureAddress Mapping in DRAM ControllerDRAM Device ArchitectureTypical DRAM Device ArchitectureSimple: 1T-1CData lo

3、sses when read or over-timeDRAM Device ArchitectureData Width of DRAM DeviceAlso the data width of each bankEach DRAM device will have several banksDRAM Device ArchitectureBank? Rank? Channel?DRAM Device ArchitectureBankDRAM Device ArchitectureRankDRAM Device ArchitectureChannelDRAM Device Architect

4、ureOverview of Bank, Rank, ChannelDRAM Device ArchitectureExample: Transfer a Cache Block 0 xFFFFF0 x000 x40.64B cache blockPhysical memory spaceChannel 0DIMM 0Rank 0Mapped toDRAM Device ArchitectureExample: Transfer a Cache Block 0 xFFFFF0 x000 x40.64B cache blockPhysical memory spaceRank 0Chip 0Ch

5、ip 1Chip 7Data 8BRow 0Col 0. . .8BDRAM Device ArchitectureExample: Transfer a Cache Block 0 xFFFFF0 x000 x40.64B cache blockPhysical memory spaceData 8B8B8BRank 0Chip 0Chip 1Chip 7Row 0Col 1. . .DRAM Device ArchitectureExample: Transfer a Cache Block 0 xFFFFF0 x000 x40.64B cache blockPhysical memory

6、 spaceData 8B8BRank 0Chip 0Chip 1Chip 7Row 0Col 1. . .A 64B cache block takes 8 I/O cycles to transfer.During the process, 8 columns are read sequentially.DRAM Basic KnowledgeDRAM Device ArchitectureDRAM Access FlowDRAM Basic CommandsDRAM Command SchedulePage ClosePage OpenBank InterleaveCommands Re

7、-OrderDRAM Controller BasicDRAM Controller Function & ArchitectureAddress Mapping in DRAM ControllerDRAM Access FlowDRAM Access Flow OverviewDRAM Access FlowDifferential Sense Amplifier Row BufferDRAM Access FlowCircuits of Differential Sense AmplifierDRAM Access FlowRead Access Step1 Word Line Sele

8、ctDRAM Access FlowRead Access Step2 Sense AmplifierDRAM Access FlowRead Access Step3 RestoreDRAM Access FlowRead Access Step4 Pre-chargeDRAM Access FlowSense Amplifier Voltage Waveform Read FlowDRAM Access FlowWrite Access FlowDRAM Basic KnowledgeDRAM Device ArchitectureDRAM Access FlowDRAM Basic Co

9、mmands & Timing ParametersDRAM Command SchedulePage ClosePage OpenBank InterleaveCommands Re-OrderDRAM Controller BasicDRAM Controller Function & ArchitectureAddress Mapping in DRAM ControllerDRAM Basic CommandsKey Timing ParametersParameterParameterDescriptionDescriptiont tRCDRCDRow to Column comma

10、nd DelayTime interval between row access command and data read at sense amplifierst tRASRASRow Access StrobeTime interval between row access command and data restoration in DRAM arrayt tCASCASColumn Access StrobeTime interval between column access command and data return by DRAM devicet tRPRPRow Pre

11、charge timeTime interval that it takes for precharge and ready for another row accesst tWRWRWrite Recovery timeMinimum time interval between write burst and precharge, restore data to cellt tRCRCRow Cycle timeTime interval between accesses to different rows in a given bankt tRFCRFCRefresh Cycle time

12、Time interval between refresh command and activation commandDRAM Basic CommandsRow Access Command Activation DRAM Basic CommandsColumn Read CommandDRAM Basic CommandsColumn Write CommandDRAM Basic CommandsPrecharge CommandDRAM Basic CommandsRefresh CommandDRAM Basic CommandsMore about DRAM RefreshTh

13、e memory controller needs to refresh each row periodically to restore chargeRead and close each row every N msTypical N = 64 msDownside of DRAM RefreshPower ConsumePerformance degradationRefresh rate limits DRAM capacity scalingDRAM Basic CommandsMore about DRAM RefreshRefresh MethodBurst refreshDis

14、tributed refreshDRAM Basic CommandsMore about DRAM RefreshDRAM Basic CommandsMore about DRAM RefreshDRAM Basic CommandsDRAM Refresh in LPDDRxTCSR Temperature Compensated Self RefreshEmbedded temperature sensor, adjust refresh period based on temperature (Also Adopted in DDR4)PASRPartial Array Self R

15、efreshOnly use part of the DRAM to save powerDRAM Basic CommandsA Read CycleDRAM Basic CommandsPower Consume in DRAM Read CycleDRAM Basic CommandsPower Related Timing Parameters tRRDtRRD : Row to Row activation Delay, different bankWill affect DRAM command schedulingDRAM Basic CommandsPower Related

16、Timing Parameters tFAWtFAW : Four Bank Activation WindowWill affect DRAM command schedulingDRAM Basic CommandsThe value of tRRD and tFAW is Page Size RelatedExample: 1Gbit DDR2 SDRAM device from MicronDRAM Basic CommandsThe Trend of tRRD and tFAWDRAM Basic CommandstRRD and tFAW in DDR4DRAM Basic Kno

17、wledgeDRAM Device ArchitectureDRAM Access FlowDRAM Basic CommandsDRAM Command SchedulePage Hit/MissPage Open/Close PolicyBank InterleaveCommands Re-OrderDRAM Controller BasicDRAM Controller Function & ArchitectureAddress Mapping in DRAM ControllerDRAM Command SchedulePage (Row Buffer) Hit/MissPage H

18、itNext Read/Write Access is in the same bank & same rowAccess Flow: Read/Write Command Data TransactionPage MissNext Read/Write Access is in the same bank & different rowAccess Flow: Precharge to the current row Active next row Read/Write Command Data TransactionDRAM Command SchedulePage (Row Buffer

19、) Hit/Miss DemoRow Buffer(Row 0, Column 0)Row decoderColumn muxRow address 0Column address 0DataRow 0Empty (Row 0, Column 1)Column address 1(Row 0, Column 85)Column address 85(Row 1, Column 0)HITHITRow address 1Row 1Column address 0CONFLICT !ColumnsRows Access Address: DRAM Command SchedulePage Open

20、Keep the row open after an accessNext access might need the same row row hitNext access might need a different row row conflict, wasted energyPage CloseClose the row after an access (if no other requests already in the request buffer need the same row)Next access might need a different row avoid a r

21、ow conflictNext access might need the same row extra activate latencyDRAM Command ScheduleBank InterleaveLow time cost when switch between different bankUse certain address mapping to increase bank interleaveAddress Mapping Example: Row : Bank : ColumnCommand ReorderReorder DRAM commands to implemen

22、t bank interleave and increase page hit rateReorder read and write access commandsGive read command a higher priorityReorder read/write command queue to increase page hit rate & bank interleaveDRAM Command ScheduleExample of Bank Interleave and Command ReorderDRAM Command SchedulePerformance Analyze

23、 of Schedule PolicyPerformance Test ScenarioPerformance Test ScenarioDual-Core, DDR266, 4 ranks per channelWeb-Server benchmark (Figure 1)Read : Write 2 : 1; Random Address (Figure 2, 3)Schedule PolicySchedule PolicyMC-A0 : Page-Open, No Bank/Rank Interleave, In-OrderMC-A1 : MC-A with Rank Interleav

24、eMC-A2 : MC-A with Bank Interleave and Page-CloseMC-B0 : Page-Close, Bank/Rank Interleave, In-OrderMC-B1 : MC-B0 with Re-Order, give read command higher priority but read/write command queue in orderMC-B2 : MC-B1 with Re-Order in Read/Write Command QueueNote:Note: The order means the order of read/w

25、rite accessThe order means the order of read/write accessDRAM Command SchedulePerformance Analyze of Schedule PolicyWeb-Server benchmarkDRAM Command SchedulePerformance Analyze of Schedule PolicyRead : Write 2 : 1Random AddressDRAM Command SchedulePerformance Analyze of Schedule PolicyRead : Write 2

26、 : 1Random AddressPart 1 - DRAM Basic KnowledgeDRAM Device ArchitectureDRAM Access FlowDRAM Basic CommandsDRAM Command SchedulePage Hit/MissPage Open/Close PolicyBank InterleaveCommands Re-OrderDRAM Controller BasicDRAM Controller Function & ArchitectureAddress Mapping in DRAM ControllerDRAM Control

27、ler BasicFunction of DRAM ControllerCorrect function of DRAMInitializationRefreshTiming LimitsSchedule the request to DRAMRe-OrderRank/Bank ManagementPower ManagementTurn On/Off DRAMSelf-RefreshDRAM Controller BasicGeneric DRAM Controller ArchitectureDRAM Controller BasicGeneric DRAM Controller Arch

28、itectureDRAM Controller BasicAddress MappingRank? Bank? Row? Column?Single-channel system with 8-byte memory bus2GB memory, 8 banks, 16K rows & 2K columns per bankRow interleavingConsecutive rows of memory in consecutive banksCache block interleavingConsecutive cache block addresses in consecutive b

29、anksReference MaterialsModern Dram Memory Systems : Performance Analysis And A High Performance, Power-constrained Dram Scheduling Algorithm, David Tawei WangMemory Access Scheduling, Scott RixnerA Study of Performance Impact of Memory ControllerFeatures in Multi-Processor Server Environment, Chitra NatarajanUnderstanding DDR4 and Todays DRAM Frontier, SAMSUNGhttp:/www.ece.cmu.edu/ece447/s13/doku.php?id=schedule