半导体制造技术光刻气相成底膜到软烘课件.pptx
- 【下载声明】
1. 本站全部试题类文档,若标题没写含答案,则无答案;标题注明含答案的文档,主观题也可能无答案。请谨慎下单,一旦售出,不予退换。
2. 本站全部PPT文档均不含视频和音频,PPT中出现的音频或视频标识(或文字)仅表示流程,实际无音频或视频文件。请谨慎下单,一旦售出,不予退换。
3. 本页资料《半导体制造技术光刻气相成底膜到软烘课件.pptx》由用户(三亚风情)主动上传,其收益全归该用户。163文库仅提供信息存储空间,仅对该用户上传内容的表现方式做保护处理,对上传内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知163文库(点击联系客服),我们立即给予删除!
4. 请根据预览情况,自愿下载本文。本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。
5. 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007及以上版本和PDF阅读器,压缩文件请下载最新的WinRAR软件解压。
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 半导体 制造 技术 光刻 相成 底膜到软烘 课件
- 资源描述:
-
1、 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSemiconductor Manufacturing TechnologyMichael Quirk & Julian Serda October 2001 by Prentice HallChapter 13 Photolithography: Surface Preparation to Soft Bake 2000 by Prentice HallSemiconductor Manufacturing
2、Technologyby Michael Quirk and Julian Serda 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaObjectivesAfter studying the material in this chapter, you will be able to:1. Explain the basic concepts for photolithography, including process overview, critical
3、dimension generations, light spectrum, resolution and process latitude.2. Discuss the difference between negative and positive lithography.3. State and describe the eight basic steps to photolithography.4. Explain how the wafer surface is prepared for photolithography.5. Describe photoresist and dis
4、cuss photoresist physical properties.6. Discuss the chemistry and applications of conventional i-line photoresist.7. Describe the chemistry and benefits of deep UV (DUV) resists, including chemically amplified resists.8. Explain how photoresist is applied in wafer manufacturing.9. Discuss the purpos
5、e of soft bake and how it is accomplished in production. 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaWafer Fabrication Process FlowImplantDiffusionTest/SortEtchPolishPhotoCompleted waferUnpatterned waferWafer startThin FilmsWafer fabrication (front-end
6、) Used with permission from Advanced Micro DevicesFigure 13.1 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian Serda Patterning Process Photomask Reticle Critical Dimension Generations Light Spectrum Resolution Overlay Accuracy Process LatitudePhotolithography C
7、oncepts 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhotomask and Reticle for MicrolithographyPhotograph provided courtesy of Advanced Micro Devices4:1 Reticle1:1 MaskPhoto 13.1 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quir
8、k and Julian SerdaThree Dimensional Pattern in PhotoresistLinewidthSpaceThicknessSubstratePhotoresistFigure 13.2 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSection of the Electromagnetic SpectrumVisibleRadio wavesMicro-wavesInfraredGamma raysUVX-raysf
9、 (Hz)1010101010101010101046810121416221820(m)420-2-4-6-8-14-10-1210101010101010101010365436405248193157ghiDUVDUVVUV (nm)Common UV wavelengths used in optical lithography.Figure 13.3 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaImportant Wavelengths for
10、Photolithography ExposureUV Wavelength(nm)WavelengthNameUV Emission Source436g-lineMercury arc lamp405h-lineMercury arc lamp365i-lineMercury arc lamp248Deep UV (DUV)Mercury arc lamp orKrypton Fluoride (KrF) excimer laser193Deep UV (DUV)Argon Fluoride (ArF) excimer laser157Vacuum UV (VUV)Fluorine (F2
11、) excimer laserTable 13.1 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaImportance of Mask Overlay AccuracyPMOSFETNMOSFETCross section of CMOS inverterTop view of CMOS inverterThe masking layers determine the accuracy by which subsequent processes can be
12、 performed. The photoresist mask pattern prepares individual layers for proper placement, orientation, and size of structures to be etched or implanted. Small sizes and low tolerances do not provide much room for error.Figure 13.4 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael
13、 Quirk and Julian SerdaPhotolithography Processes Negative Resist Wafer image is opposite of mask image Exposed resist hardens and is insoluble Developer removes unexposed resist Positive Resist Mask image is same as wafer image Exposed resist softens and is soluble Developer removes exposed resist
14、2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaNegative LithographyUltraviolet lightIslandAreas exposed to light become crosslinked and resist the developer chemical.Resulting pattern after the resist is developed.WindowExposed area of photoresistShadow o
15、n photoresistChrome island on glass maskSilicon substratePhotoresistOxidePhotoresistOxideSilicon substrateFigure 13.5 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPositive LithographyFigure 13.6 photoresistsilicon substrateoxideoxidesilicon substratepho
16、toresistUltraviolet lightIslandAreas exposed to light are dissolved.Resulting pattern after the resist is developed.Shadow on photoresistExposed area of photoresistChrome island on glass maskWindowSilicon substratePhotoresistOxidePhotoresistOxideSilicon substrate 2001 by Prentice HallSemiconductor M
17、anufacturing Technologyby Michael Quirk and Julian SerdaRelationship Between Mask and ResistDesired photoresist structure to be printed on wafer WindowSubstrateIsland of photoresistQuartzChromeIslandMask pattern required when using negative photoresist (opposite of intended structure)Mask pattern re
18、quired when using positive photoresist (same as intended structure)Figure 13.7 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaClear Field and Dark Field MasksSimulation of contact holes(positive resist lithography)Simulation of metal interconnect lines(po
19、sitive resist lithography)Clear Field MaskDark Field MaskFigure 13.8 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaEight Steps of PhotolithographyTable 13.2 StepChapter1. Vapor prime132. Spin coat133. Soft bake134. Alignment and exposure145. Post-exposur
20、e bake (PEB)156. Develop157. Hard bake158. Develop inspect15 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaEight Steps of Photolithography8) Develop inspect5) Post-exposure bake6) Develop7) Hard bakeUV LightMask4) Alignment and ExposureResist2) Spin coat
21、3) Soft bake1) Vapor primeHMDSFigure 13.9 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhotolithography Track SystemPhoto courtesy of Advanced Micro Devices, TEL Track Mark VIIIPhoto 13.2 2001 by Prentice HallSemiconductor Manufacturing Technologyby Mic
22、hael Quirk and Julian SerdaVapor PrimeThe First Step of Photolithography: Promotes Good Photoresist-to-Wafer Adhesion Primes Wafer with Hexamethyldisilazane, HMDS Followed by Dehydration Bake Ensures Wafer Surface is Clean and Dry 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael
23、 Quirk and Julian SerdaSpin CoatProcess Summary:Wafer is held onto vacuum chuckDispense 5ml of photoresistSlow spin 500 rpmRamp up to 3000 to 5000 rpmQuality measures: time speed thickness uniformity particles and defectsVacuum chuckSpindle connected to spin motorTo vacuum pumpPhotoresist dispenserF
24、igure 13.10 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSoft bakeCharacteristics of Soft Bake: Improves Photoresist-to-Wafer Adhesion Promotes Resist Uniformity on Wafer Improves Linewidth Control During Etch Drives Off Most of Solvent in Photoresist T
25、ypical Bake Temperatures are 90 to 100C For About 30 Seconds On a Hot Plate Followed by Cooling Step on Cold Plate 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaAlignment and ExposureProcess Summary:Transfers the mask image to the resist-coated waferActi
展开阅读全文